References
- Z. Al-Ars and A. J. van de Goor, "Soft faults and importance of stresses in memory testing," Design, Automation and Test in Europe Conference and Exhibition, pp. 1084-1089, Feb. 2004.
- R. C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," Device and Materials Reliability, IEEE Transactions on, vol. 5, pp. 305-316, 2005. https://doi.org/10.1109/TDMR.2005.853449
- P. E. Dodd, M. R. Shaneyfelt, J. R. Schwank, and J. A. Felix, "Current and future challenges in radiation effects on CMOS electronics," Nuclear Science, IEEE Transactions on, vol. 57, pp. 1747-1763, 2010. https://doi.org/10.1109/TNS.2010.2042613
- R. W. Hamming, "Error detecting and error correcting code," Bell System Technical Journal, vol. 26, pp. 147-160, Apr.1950.
- M. Y. Hsiao, "A class of optimal minimum oddweight- column SEC-DED codes," Research and Development, IBM Journal of, vol. 14, Issue 4, pp. 395-401, Jul. 1970. https://doi.org/10.1147/rd.144.0395
- Eiji Fujiwara, "Code design for dependable systems - Theory and practical applications," Wiley-interscience, 2006.
- S. Cha, Y. Lee, and H. Yoon, "A low-power ECC check bit generator implementation in DRAMs," Journal of Semiconductor Technology and Science, vol. 6, no. 4, pp. 252-256, Dec. 2006.
- P. K. Lala, P. Thenappan, and M. T. Anwar, "Single error correcting and double error detecting coding scheme," IET Electronics Letters, vol. 41, Issue 13, pp. 758-760, Feb. 2005. https://doi.org/10.1049/el:20050614
- S. Cha and H. Yoon, "High speed, minimal area, and low power SEC code for DRAMs with large I/O data widths," Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 3026-3029, May 2007.
- B. Polianskikh and Z. Zilic, "Design and implementation of error detection and correction circuitry for multilevel memory protection," Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on, pp. 89-95, 2002.
- W. Gao and S. Simmons, "A study on the VLSI implementation of ECC for embedded DRAM," Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on, vol. 1, pp. 203-206, 2003.
- M. Nicolaidis, T. Bonnoit, and N.-E. Zergainoh, "Eliminating speed penalty in ECC protected memories," Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1-6, 2011.
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