전기전자학회논문지 (Journal of IKEEE)

  • 제15권2호
  • /
  • Pages.134-142
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  • 2011
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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3중 모드 DC-DC 벅 변환기 설계

Design of a Tripple-Mode DC-DC Buck Converter

  • Yu, Seong-Mok (Dept. of Electronics Engineering, University of Incheon) ;
  • Park, Joon-Ho (Dept. of Electronics Engineering, University of Incheon) ;
  • Park, Jong-Tae (Dept. of Electronics Engineering, University of Incheon) ;
  • Yu, Chong-Gun (Dept. of Electronics Engineering, University of Incheon)
  • 투고 : 2011.06.02
  • 발행 : 2011.06.30
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 3중 모드 고효율 DC-DC 벅 변환기를 설계하였다. 설계된 벅 변환기는 부하 전류가 큰 경우(100mA~500mA)에는 PWM(Pulse Width Modulation) 제어 방식을 사용하고, 부하 전류가 작은 경우(1mA~100mA)에는 PFM(Pulse Frequency Modulation) 제어 방식을 사용하며, 부하 전류가 1mA 이하인 대기모드(sleep mode)에서는 LDO(Low Drop Out)를 사용한다. 또한, PFM 모드에서 부하 전류가 작은 경우 효율을 증가시키기 위해 DPSS(Dynamic Partial Shutdown Strategy) 기법을 사용하였다. 그 결과 설계된 변환기는 넓은 부하 전류 범위에서 높은 효율을 얻을 수 있다. 제안된 벅 변환기는 CMOS 0.18um공정을 이용하여 설계되었다. 최대 효율은 96.4% 이고, 최대 부하 전류는 500mA이다. 입력과 출력 전압은 각각 3.3V와 2.5V이며, 칩 크기는 PAD를 포함하여 1.15mm ${\times}$ 1.10mm이다.

This paper describes a tripple-mode high-efficiency DC-DC buck converter. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(100mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~100mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 96.4% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is 1.15mm ${\times}$ 1.10mm including pads.

키워드

참고문헌

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