전기전자학회논문지 (Journal of IKEEE)

  • 제15권1호
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  • Pages.29-36
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  • 2011
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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WLAN 응용을 위한 DAC를 이용한 Digitally Controlled LC Oscillator 설계

Design of a Digitally Controlled LC Oscillator Using DAC for WLAN Applications

  • 투고 : 2011.03.04
  • 발행 : 2011.03.31
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⟨ 이전 논문 다음 논문 ⟩

초록

기존에 ADPLL(All Digital Phase Locked Loop)에서는 DCO(Digitally Controlled Oscillator)의 해상도를 향상시키기 위해 주로 dithering 기법이 사용되었다. 본 논문에서는 dithering 방식에서 발생하는 문제점을 보안하고자 DAC를 이용한 DCO의 해상도 확보 방법을 제안하였다. $0.13{\mu}m$ CMOS 공정을 이용하여 고해상도의 2.4GHz LC DCO를 무선 로컬 네트워크 통신에 적용 가능하도록 설계하였다. 설계된 DCO는 900MHz의 주파수 튜닝 범위를 가지고 발진하며 58.8Hz의 해상도를 보여준다. 주파수 컨트롤은 coarse, fine, DAC 배랙터 bank에 의해서 이루어지며, coarse와 fine bank는 PMOS 배랙터로, DAC bank는 NMOS 배랙터로 구성되었다. 각 배랙터 bank는 8비트의 디지털 입력으로 컨트롤된다. 설계된 DCO의 위상잡음은 1MHz 옵셋에서 -123.8dBc/Hz이다. 설계된 DCO는 공급전압 1.2V에서 4.2mA의 전류를 소모한다.

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

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참고문헌

  1. J. Dunning et al., "An All-Digital Phase Locked Loop with 50-cycle Lock Time Suitable for High performance Microprocessors," IEEE J. Solid State Circuits, vol. 30, pp. 312-422, Apr. 1955
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  3. Luca Fanori et al., "3.3GHz DCO with a Frequency Resolution of 150Hz for All-Digital PLL," IEEE International Solid-State Circuits Conference, pp. 48-49, Feb. 2010
  4. Jurgen Deveugele et al., "A Gradient-Error and Edge-Effect Tolerant Switching Scheme for a High- Accuracy DAC," IEEE Transactions on Circuits and Systems vol. 51, no. 1, pp. 191-195, Jan. 2004 https://doi.org/10.1109/TCSI.2003.821307
  5. Jingcheng Zhuang, Qingjin Du, Tad Kwasniewski, "A 3.3 GHz LC-Based Digitally Controlled Oscillator with 5kHz Frequency Resolution," IEEE Asian Solid State Circuits, pp. 428 - 431, Nov. 2007
  6. Liangge Xu, Saska Lindfors, "A Digitally Controlled 2.4-GHz Oscillator in 65-nm CMOS," IEEE Digital Object Identifier, Norchip, pp. 1-4, Nov. 2007
  7. Ping Lu and Henrik Sjoland, "A 5.4GHz 90-nm CMOS Digitally Controlled LC Oscillator with 21% Tuning Range, 1.1MHz resolution, and 180dB FOM," IEEE Norchip, pp. 223-226, Nov. 2008