Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Design of a High-Resolution DCO Using a DAC

DAC를 이용한 고해상도 DCO 설계

  • Received : 2011.02.13
  • Accepted : 2011.03.04
  • Published : 2011.07.31
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Abstract

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

기존에 ADPLL(All Digital Phase Locked Loop)에서는 DCO(Digitally Controlled Oscillator)의 해상도를 향상시키기 위해 주로 디더링(dithering) 기법이 사용되었다. 본 논문에서는 디더링 방식에서 발생하는 문제점을 보안하고자 DAC(Digital-to-Analog Converter)를 이용한 DCO의 해상도 확보 방법을 제안하였다. 주파수 컨트롤은 coarse와 fine 바랙터(varactor) bank 그리고 DAC 바랙터에 의해서 이루어지며, coarse와 fine bank는 PMOS 바랙터로, DAC 바랙터는 NMOS 바랙터로 구현하였다. 각 바랙터 bank는 8비트의 디지털 입력으로 컨트롤된다. $0.13{\mu}m$ CMOS 공정을 이용하여 설계된 DCO는 약 2.8GHz~3.5GHz의 주파수 범위에서 발진하며 660MHz의 대역폭을 갖는다. DCO의 출력 주파수를 측정한 결과 해상도는 2.8GHz대역에서 73Hz이다. 설계된 DCO는 1M 옵셋(offset)에서 -119dBc/Hz의 위상 잡음 특성을 보이며, 1.2V 전원에서 4.2mA의 전류를 소모한다. 칩 면적은 PAD를 포함하여 $1.3mm{\times}1.3mm$이다.

Keywords

References

  1. J. Dunning et al., "An All-Digital Phase Locked Loop with 50-cycle Lock Time Suitable for High performance Microprocessors," IEEE J. Solid State Circuits, vol. 30, pp. 312-422, Apr. 1955.
  2. R. B. Staszewski et al., "A first multi gigahertz digitally controlled oscillator for wireless applications," IEEE Transactions on Microwave theory and techniques, vol. 51, no. 11, pp. 2154-2164, Nov. 2003. https://doi.org/10.1109/TMTT.2003.818579
  3. L. Fanori et al., "3.3GHz DCO with a Frequency Resolution of 150Hz for All-Digital PLL," IEEE International Solid-State Circuits Conference, pp. 48-49, Feb. 2010.
  4. J. Deveugele et al., "A Gradient-Error and Edge-Effect Tolerant Switching Scheme for a High-Accuracy DAC," IEEE Transactions on Circuits and Systems, vol. 51, no. 1, pp. 191-195, Jan. 2004. https://doi.org/10.1109/TCSI.2003.821307
  5. G. Van der Plaset et al., "A 14-bit intrinsic accuracy random walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 34, pp. 1708-1718, Dec. 1999. https://doi.org/10.1109/4.808896
  6. J. Zhuang, Q. Du, T. Kwasniewski, "A 3.3 GHz LC-Based Digitally Controlled Oscillator with 5kHz Frequency Resolution," IEEE Asian Solid State Circuits, pp. 428-431, Nov. 2007.
  7. L. Xu, S. Lindfors, "A Digitally Controlled 2.4-GHz Oscillator in 65-nm CMOS," IEEE Digital Object Identifier, Norchip, pp. 1-4, Nov. 2007.
  8. P. Lu and H. Sjoland, "A 5.4GHz 90-nm CMOS Digitally Controlled LC Oscillator with 21% Tuning Range, 1.1MHz resolution, and 180dB FOM," IEEE Norchip, pp. 223-226, Nov. 2008.