DOI QR코드

DOI QR Code

Cu Filling into TSV and Si Dice Stacking for 3 Dimension Packaging

3차원 실장을 위한 TSV의 Cu 충전 및 Si 칩 적층 기술

  • Published : 2011.06.30

Abstract

Keywords

References

  1. J. H. Lau, "Evolution and Outlook of TSV and 3D IC/Si Integration", 12th Electronics Packaging Technology Conference, EPTA 2010, (2010), 560-570
  2. S. J. Hong, Y. W. Lee, K. S. Kim, K. J. Lee, J. O. Kim, J. H. Park, and J. P. Jung : Filling via hole in Si-wafer for 3 Dimensional Packaging, The Korean Welding and Joining Society Conference, 2006 (in Korean)
  3. J. H. Jun, I. R Kim, M. Mayer, Y. N. Zhou, S. B. Jung, and J. P. Jung, "A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging", Materials Transactions, 51-10 (2010), 1887-1892 https://doi.org/10.2320/matertrans.M2009314
  4. I. R. Kim, J. K. Park, Y. C. Chu, and J. P. Jung : High Speed Cu Filling Into TSV by Pulsed Current for 3 Dimensional Chip Stacking, Kor. J. Met. Mater., 48-7 (2010), 667-673 (in Korean)
  5. F. Inoue, T. Shimizu, T. Yokoyama, H. Miyake, K. Kondo, T. Saito, T. Hayashi, S. Tanaka, T. Terui, and S. Shingubara : Formation of electroless barrier and seed layers in a high aspect ratio through-Si vias using Au nanoparticle catalyst for all-wet Cu filling technology, Electrochimica Acta, 56 (2011), 6245-6250 https://doi.org/10.1016/j.electacta.2011.02.078
  6. T. Luah, C. T. Su, T. H. Yang, K. C. Chen, and C. Y. Lu : Advanced tungsten plug process for beyond nanometer technology, Microelectronic Engineering, 85 (2008), 1739-1747 https://doi.org/10.1016/j.mee.2008.04.030
  7. E. M. Chow, V. Chandrasekaran, A. Partridge, T. Nishida, M. Sheplak, C. F. Quate, and T. W. Kenny. : Process Compatible Polysilicon-Based Electrical Through-Wafer Interconnects in Silicon Substrates, J. Micro Electromechanical Sys., 11-6 (2002), 631-640 https://doi.org/10.1109/JMEMS.2002.805206
  8. T. Takizawa, S. Yamamoto, K. Otsubo, and A. Kawasaki : Conductive interconnections through thick silicon substrates for 3D packaging, Proceedings of the IEEE Micro Electro Mechanical Systems (MEMS), 2002, 388-391 https://doi.org/10.1109/MEMSYS.2002.984284
  9. P. Dixit, X. Chen, J. Miao, S. Divakaran, and R. Preisser : Study of surface treatment processes for improvement in the wettability of silicon-based materials used in high aspect ratio through-via copper electroplating, Applied Surface Science, 253 (2007), 8637-8646 https://doi.org/10.1016/j.apsusc.2007.04.067
  10. A. Pohjoranta and R. Tenno : A method for microvia-fill process modeling in a Cu plating system with additives, J. Electrochemical Soc., 154 (2007), D502-D509 https://doi.org/10.1149/1.2761638
  11. B. O. Lim, K. S. Choi, Y. S. Eom, H. C. Bae, S. Jung, K. J. Sung, and J. T. Moon . : Optimized TSV Process Using Bottom-Up Electroplating without Wafer Cracks, Electronic Components and Technology Conference, 2010, 1642-1646
  12. S. J. Hong, S. C. Hong, W. J. Kim, and J. P, Jung : Copper Filling to TSV (Through-Si-Via) and Simplification of Bumping Process, Journal of the Microelectronics & Packaging Society, 17-3 (2010), 79-84 (in Korean)
  13. S. J. Hong, J. H. Jun, J. P. Jung, M. Mayer, and Y. Norman Zhou : Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3-D Packaging, IEEE Transactions on advanced packaging, 22-4 (2010), 912-917 https://doi.org/10.1109/TADVP.2010.2049019
  14. D. R. Flanders, E. G. Jacobs, and R. F. Pinizzotto : Acivation energies of intermetallic growth of Sn-Ag eutectic solder on copper substrates, J. electron. Mater., 26-7 (1997), 883-887 https://doi.org/10.1007/s11664-997-0268-4
  15. T. Morifuji, Y. Tomita, T. sato, and K. Takahashi : High accuracy interconnection technologies on 3-D stacking Process, in Proc. MATE, (2001), 113-118 (in Japanese)