Journal of the Institute of Electronics Engineers of Korea CI (전자공학회논문지CI)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient Cache Architecture for Transactional Memory

트랜잭셔널 메모리를 위한 효율적인 캐시 구조

  • Choi, Dong-Min (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Seung-Hun (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Ro, Won-Woo (Department of Electrical and Electronic Engineering, Yonsei University)
  • 최동민 (연세대학교 전기전자공학과) ;
  • 김승훈 (연세대학교 전기전자공학과) ;
  • 노원우 (연세대학교 전기전자공학과)
  • Received : 2011.05.26
  • Accepted : 2011.06.30
  • Published : 2011.07.25
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Abstract

Traditional transactional memory systems are no longer able to guarantee the performance of diverse applications with overflowed transactions since there is the drawback that tracking the data for logging is difficult. Especially, this mechanism has a disadvantage of increasing communication delay for sustaining the state which is required to detect the conflict on the overflowed transactions from the first level cache in the transactional memory systems. To address this point, we have focused on the cache architecture of the systems to reduce the overhead caused by overflows and cache misses. In this paper, we present Supportive Cache which reduces additional overhead during transactions. Supportive Cache performs a parallel look-up with L1 private cache and uses the same replacement policy as L1 private cache. We evaluate the performance of the proposed design by comparing LogTM-SE with and without Supportive Cache. The simulation results show that our system improves the performance by 37% on average, compared to the original LogTM-SE which uses the same hardware resource.

트랜잭셔널 메모리 시스템에서 오버플로우(overflow) 발생 시 이를 처리하기 위한 데이터의 기록은 그 복잡성으로 인해 전체 시스템 성능 저하의 주요 요인이 된다. 특히, 오버플로우 된 데이터가 일으킬 수 있는 충돌감지를 위해 캐시 일관성 프로토콜 상에 추가적인 상태 설정이 요구되며 이로 인해 트랜잭션간 커뮤니케이션에 지연이 발생한다. 이러한 문제점을 해결하기 위해 우리는 트랜잭셔널 메모리 시스템에서 오버플로우에 의해 발생하는 오버 헤드를 줄이기 위한 효율적인 캐시 구조를 연구하였다. 본 논문에서 제안하는 보조 캐시(supportive cache)는 1차 캐시와 동일한 교체 정책을 사용하며 병렬 룩업이 가능하도록 작동한다. 보조 캐시의 성능 평가를 위해 하드웨어 트랜잭셔널 메모리 시스템인 LogTM-SE를 사용하였으며 시뮬레이션 결과 평균적으로 37%의 성능 향상을 보였다.

Keywords

References

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