JSTS:Journal of Semiconductor Technology and Science

  • 제11권4호
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  • Pages.309-317
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  • 2011
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Design of Baseband Analog Chain with Optimum Allocation of Gain and Filter Rejection for WLAN Applications

  • Cha, Min-Yeon (Division of Electrical and Computer Engineering, College of Information Technology, Ajou University) ;
  • Kwon, Ick-Jin (Division of Electrical and Computer Engineering, College of Information Technology, Ajou University)
  • 투고 : 2011.06.07
  • 발행 : 2011.12.31
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초록

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

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참고문헌

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