JSTS:Journal of Semiconductor Technology and Science

  • 제11권4호
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  • Pages.272-277
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  • 2011
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Ambipolarity Factor of Tunneling Field-Effect Transistors (TFETs)

  • Jang, Jung-Shik (Department of Electronic Engineering, Sogang University) ;
  • Choi, Woo-Young (Department of Electronic Engineering, Sogang University)
  • 투고 : 2011.07.17
  • 발행 : 2011.12.31
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초록

The ambipolar behavior of tunneling field-effect transistors (TFETs) has been investigated quantitatively by introducing a novel parameter: ambipolarity factor (${\nu}$). It has been found that the malfunction of TFET can result from the ambipolar state which is not on- or off- state. Therefore, the effect of ambipolar behavior on the device performance should be parameterized quantitatively, and this has been successfully evaluated as a function of device structure, gate oxide thickness, supply voltage, drain doping concentration and body doping concentration by using ${\nu}$.

키워드

참고문헌

  1. P. -F. Wang, K. Hilsenbeck, Th. Nirschl, M. Oswald, Ch. Stepper, M. Weis, D. Schmitt- Landsiedel, W. Hansch, "Complementary Tunneling Transistor for Low Power Application," Solid-State Electronics, Vol.48, No.12, pp.2281- 2286, Dec., 2004. https://doi.org/10.1016/j.sse.2004.04.006
  2. K. K. Bhuwalka, J. Schulze, I. Eisele, "Scaling the Vertical Tunnel FET with Tunnel Bandgap Modulation and Gate Workfunction Engineering," Electron Devices, IEEE Transactions on, Vol.52, No.5, pp.909-917, May., 2005. https://doi.org/10.1109/TED.2005.846318
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  4. A. S. Verhulst, W. G. Vandenberghe, K. Maex, G. Groeseneken, "Tunnel Field-Effect Transistor without Gate-Drain Overlap," Applied Physics Letters, Vol.91, No.5, pp.053102-1-053102-3, Jul., 2007. https://doi.org/10.1063/1.2757593
  5. W. Y. Choi, B. -G. Park, J. D. Lee, T. -J. K. Liu, "Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less Than 60 mV/dec," Electron Device Letters, IEEE, Vol.28, No.8, pp.743-745, Aug., 2007. https://doi.org/10.1109/LED.2007.901273
  6. V. Nagavarapu, R. Jhaveri, J.C.S. Woo, "The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor," Electron Devices, IEEE Transactions on, Vol.55, No.4, pp.1013-1019, Apr., 2008. https://doi.org/10.1109/TED.2008.916711
  7. C. Hu, D. Chou, P. Patel, A. Bowonder, "Green Transistor - A VDD Scaling Path for Future Low Power ICs," VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on, 21-23, pp.14-15, Apr., 2008.
  8. T. Krishnamohan, D. Kim, S. Raghunathan, K. Saraswat, "Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and <60 mV/dec Subthreshold Slope," Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 15-17, pp.947-949, Dec., 2008.
  9. W. Y. Choi, "Comparative Study of Tunneling Field-Effect Transistors and Metal-Oxide- Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, Vol.49, No.4, pp.04DJ12-1-04DJ12-3, Apr., 2010. https://doi.org/10.1143/JJAP.49.04DJ12
  10. W. Y. Choi, W. Lee, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," Electron Devices, IEEE Transactions on, Vol.57, No.9, pp.2317-2319, Sep., 2010. https://doi.org/10.1109/TED.2010.2052167
  11. Atlas User's Manual, Silvaco, Santa Clara, CA, Jul. 2010.

피인용 문헌

  1. L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications vol.E96.C, pp.5, 2013, https://doi.org/10.1587/transele.E96.C.634
  2. -Modulation of Planar Tunnel Field-Effect Transistors with Ground-Plane under Ultrathin Body and Bottom Oxide vol.14, pp.2, 2014, https://doi.org/10.5573/JSTS.2014.14.2.139
  3. Comparative Performance Analysis of the Dielectrically Modulated Full- Gate and Short-Gate Tunnel FET-Based Biosensors vol.62, pp.3, 2015, https://doi.org/10.1109/TED.2015.2390774
  4. Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) vol.3, pp.1, 2016, https://doi.org/10.1186/s40580-016-0073-y
  5. Monolithic three-dimensional tunnel FET–nanoelectromechanical hybrid reconfigurable logic circuits vol.56, pp.4S, 2017, https://doi.org/10.7567/JJAP.56.04CD12
  6. Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications vol.12, pp.4, 2012, https://doi.org/10.5573/JSTS.2012.12.4.482
  7. Reduction of ambipolar characteristics of vertical channel tunneling field-effect transistor by using dielectric sidewall vol.28, pp.11, 2013, https://doi.org/10.1088/0268-1242/28/11/115002