JSTS:Journal of Semiconductor Technology and Science

  • 제11권3호
  • /
  • Pages.182-189
  • /
  • 2011
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology

  • Cho, Seong-Jae (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University) ;
  • Sun, Min-Chul (Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Kim, Ga-Ram (Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Kamins, Theodore I. (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University) ;
  • Park, Byung-Gook (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University) ;
  • Harris, James S. Jr. (Department of Electrical Engineering and Center for Integrated Systems (CIS), Stanford University)
  • 투고 : 2011.05.31
  • 발행 : 2011.09.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

키워드

참고문헌

  1. W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less than 60 mV/dec," IEEE Electron Device Lett., Vol.28, No.8, Aug., 2007.
  2. P.-F. Guo, L.-T. Yang, Y. Yang, L. Fan, G.-Q. Han, G. S. Samudra, and Y.-C. Yeo, "Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current," IEEE Electron Device Lett., Vol.30, No.9, Sep., 2009.
  3. W. Y. Choi, "Comparative Study of Tunneling Field-Effect Transistors and Metal-Oxide- Semiconductor Field-Effect Transistors," Jpn. J. Appl. Phys., Vol.49, No.4, pp.04DJ12-1-04DJ12-3, Apr., 2010. https://doi.org/10.1143/JJAP.49.04DJ12
  4. E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, "Device Physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications," J. Appl. Phys., Vol.103, No.10, pp.104504-1-104504-5, May, 2008. https://doi.org/10.1063/1.2924413
  5. J. Knoch and J. Appenzeller, "Modeling of High- Performance p-Type III-V Heterojunction Tunnel FETs," IEEE Electron Device Lett., Vol.31, No.4, Apr., 2010.
  6. K. Ganapathi and S. Salahuddin, "Heterojunctino Vertical Band-to-Band Tunneling Transistors for Steep Subthreshold Swing and High ON Current," IEEE Electron Device Lett., Vol.32, No.5, pp.689- 691, May, 2011. https://doi.org/10.1109/LED.2011.2112753
  7. ATLAS User's Manual, Silvaco International, Santa Clara, CA, Nov/Dec., 2008.
  8. Process Integration, Devices & Structures (PIDS), International Technology Roadmap for Semiconductors (ITRS), 2009 edition.
  9. Y. Apanovich, P. Blakey, R. Cottle, E. Lyumkis, B. Polsky, A. Shur, and A. Tcherniaev, "Numerical simulation of submicrometer devices including coupled nonlocal transport and nonisothermal effects," IEEE Trans. Electron Devices, Vol.42, No.2, pp.890-898, May, 1995. https://doi.org/10.1109/16.381985
  10. O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, "Design of Tunneling Field-Effect Transistors Using Strained -Silicon/Strained-Germanium Type-II Staggered Heterojunctions," IEEE Electron Device Lett., Vol.29, No.9, pp.1074-1077, Sep., 2008. https://doi.org/10.1109/LED.2008.2000970
  11. M.-H. Juang, P.-S. Hu, and S.-L. Jang, "Formation of lateral SiGe tunneling field-effect transistors on the SiGe/oxide/Si-substrate," Semicond. Sci. Technol., Vol.24, No.2, pp.025019-1-025019-4, Feb., 2009. https://doi.org/10.1088/0268-1242/24/2/025019
  12. G. B. Stringfellow, "Electron mobility in $Al_{x}Ga_{1}-_{x}As$," J. Appl. Phys., Vol.50, No.6, pp.4178-4183, Jun., 1979. https://doi.org/10.1063/1.326445
  13. A. K. Saxena, "Electron mobility in $Ga_{1-x}AL_{x}As$ alloys," Phys. Rev. B: Condens. Matter, Vol.24, No.6, pp.3295-3302, Sep., 1981. https://doi.org/10.1103/PhysRevB.24.3295

피인용 문헌

  1. Dependency of Tunneling Field-Effect Transistor(TFET) Characteristics on Operation Regions vol.11, pp.4, 2011, https://doi.org/10.5573/JSTS.2011.11.4.287
  2. Design optimization of vertical double-gate tunneling field-effect transistors vol.61, pp.10, 2012, https://doi.org/10.3938/jkps.61.1679
  3. Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric vol.13, pp.3, 2013, https://doi.org/10.5573/JSTS.2013.13.3.224
  4. -Modulation of Planar Tunnel Field-Effect Transistors with Ground-Plane under Ultrathin Body and Bottom Oxide vol.14, pp.2, 2014, https://doi.org/10.5573/JSTS.2014.14.2.139
  5. Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor vol.54, pp.9, 2015, https://doi.org/10.7567/JJAP.54.094202
  6. Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior vol.122, pp.11, 2016, https://doi.org/10.1007/s00339-016-0510-0
  7. Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications vol.16, pp.2, 2016, https://doi.org/10.5573/JSTS.2016.16.2.172
  8. Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications vol.23, pp.9, 2017, https://doi.org/10.1007/s00542-016-2872-9
  9. Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications vol.12, pp.4, 2012, https://doi.org/10.5573/JSTS.2012.12.4.482
  10. Effect of Ga fraction in InGaAs channel on performances of gate-all-around tunneling field-effect transistor vol.30, pp.1, 2014, https://doi.org/10.1088/0268-1242/30/1/015006
  11. Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure vol.57, pp.4S, 2018, https://doi.org/10.7567/JJAP.57.04FG03
  12. composites for enhancing the photocatalytic activity toward the degradation of tetracycline vol.42, pp.7, 2018, https://doi.org/10.1039/C7NJ05123A