대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

채널 3.2/6.4 Gbps 이중 전송률 송신기

4-Channel 3.2/6.4-Gbps Dual-rate Transmitter

  • 김두호 (연세대학교 전기전자공학과) ;
  • 최우영 (연세대학교 전기전자공학과)
  • Kim, Du-Ho (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Choi, Woo-Young (Department of Electrical and Electronic Engineering, Yonsei University)
  • 투고 : 2010.04.08
  • 심사 : 2010.07.01
  • 발행 : 2010.07.25
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초록

영상데이터의 용량이 늘어남에 따라, 시리얼 링크의 전송속도는 점점 빨라지고 있다. 따라서 기존에 제시되었던 상용화규격도 계속해서 전송속도를 상향시킨 차기 버전을 제안하고 있다. 차기 버전은 기존 버전과 호환성을 갖춰야 하므로 두 가지 이상의 전송속도로 동작할 수 있는 송수신기 회로가 필요하다. 본 논문에서는 4개의 채널을 가지며, 3.2 Gb/s 또는 6.4 Gb/s의 전송속도로 동작하는 송신기를 설계하였다. 이 송신기는 1, 1.5, 2, 3배의 pre-emphasis를 선택적으로 사용할 수 있으며, 출력 스윙을 200, 300, 400, 600 mVdiff,p2p로 선택할 수 있다. 설계된 송신기는 $0.13{\mu}m$ CMOS 공정을 이용하여 제작되었으며, COB 패키징을 이용하여 PCB에 실장되어 검증되었다.

As the speed of A/V streaming, the transmission-speed requirement of serial link is continuously increasing. Consequently, commercial standards, which are released previously, are increasing transmission speed in their newly-updated versions. The flexibility between previous and updated versions is very important requirement, therefore, the transceiver which can operates at more than one data rate is important market demand. This paper demonstrates 4-channel 3.2/ 6.4 Gbps transmitter, which is capable of selecting 1, 1.5, 2, and 3 times of pre-emphasis and 200, 300, 400, and 600 mVdiff,p2p of output swing. The prototype chip was fabricated using $0.13{\mu}m$ CMOS process. Its performances are verified on PCB using COB packaging.

키워드

과제정보

연구 과제번호 : 차세대 초고속 테스터를 위한 ASIC Chip 개발

연구 과제 주관 기관 : 한국산업기술평가관리원

참고문헌

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