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FSM을 이용한 수정된 유클리드 알고리즘 설계

A Design of Modified Euclidean Algorithm using Finite State Machine

  • 강성진 (한국기술교육대학교 정보기술공학부)
  • Kang, Sung-Jin (School of Info. Tech. Engineering, Korea University of Tech. and Educ.)
  • 투고 : 2010.03.29
  • 심사 : 2010.06.18
  • 발행 : 2010.06.30

초록

본 논문에서는 FSM(finite-state machine)을 이용하여 차수 계산(degree computation)을 하지 않고 수정된 유클 리드 알고리즘(modified Euclidean algorithm)을 구현할 수 있는 구조를 제안한다. 제안된 구조는 차수계산이 필요없기 때문에 RS(Reed-Solomon) 복호기의 하드웨어 복잡도를 줄일 수 있고, 고속의 복호기 설계가 가능하게 된다. 제안된 구조를 이용하는 RS(255,239) 복호기를 Verilog HDL로 구현하였고, 기존의 복호기에 비해 게이트 수를 약 13%정도 줄일 수 있다.

In this paper, an architecture for modified Euclidean(ME) algorithm is proposed, which is using finite-state machine(FSM) instead of degree computation. Since the proposed architecture does not have degree computation circuits, it is possible to reduce the hardware complexity of RS(Reed-Solomon) decoder, so that a very high-speed RS decoder can be implemented. RS(255,239) decoder with the proposed architecture is implemented using Verilog-HDL and requires about 13% fewer gate counts than conventional one.

키워드

참고문헌

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