한국항행학회논문지 (Journal of Advanced Navigation Technology)

  • 제14권5호
  • /
  • Pages.710-717
  • /
  • 2010
  • /
  • 1226-9026(pISSN)
  • /
  • 2288-842X(eISSN)
한국항행학회 (The Korean Navigation Institute)
권호 표지

치환리터럴에 의한 Quaternary Galois Field Sum-Of-Product(QGFSOP)형 1-변수 함수의 합성과 실현

Syntheses and realization of Quaternary Galois Field Sum-Of-Product(QGFSOP) expressed 1-variable functions Permutational Literals

  • 박동영 (강릉원주대학교 정보통신공학과) ;
  • 김백기 (강릉원주대학교 정보통신공학과) ;
  • 성현경 (상지대학교 컴퓨터정보공학부)
  • Park, Dong-Young (Dept. of Information & Telecommunication Eng., Gangneung-Wonju National University) ;
  • Kim, Baek-Ki (Dept. of Information & Telecommunication Eng., Gangneung-Wonju National University) ;
  • Seong, Hyeun-Kyeong (School of Computer, Information and Communication, Sang-Ji University)
  • 투고 : 2010.08.16
  • 심사 : 2010.10.30
  • 발행 : 2010.10.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Quaternary 논리에서 생성 가능한 1-qudit(1-variable quantum digit) 함수는 총 256개가 존재하지만 이들 중에서 가장 유용한 것은 "0,1,2,3"의 치환에 의해 $Ax^C$+D(GF4)형의 QGFSOP 표현이 가능한 24개이다. 본 논문에서는 24개 1-qudit 함수들의 $Ax^C$+D(GF4) 연산에서 피연산자인 피승수 A와 피기수 D를 다단 종속된 치환리터럴의 제어인자로 사용하는 치환리터럴(Permutational Literals, PL) 표현과 QPL(Quaternary PL) gate를 제안하였다. 그리고 상호치환 'ab', 가산 '+D', 그리고 승산 'xA'과 같은 세 개의 PL 연산자를 사용하여 QGFSOP 표현된 24개 (1-qudit) 함수를 합성하기 위한 PL 합성법을 제안하였다. 끝으로 PL 합성법을 실현하기 위한 $Ax^C$+D(GF4) 구조와 연산회로 및 CMOS 실현 방법을 제시하였다.

Even though there are 256 possible 1-qudit(1-variable quantum digit) functions in quaternary logic, the most useful functions are 4!=24 ones capable of representing in QGFSOP expressions by possible permuting of 0,1,2, and 3. In this paper, we propose a permutational literal(PL) representation and a QPL(Quaternary PL) gate which use the operands of a multiplicand A and an augend D in $Ax^C$+D(GF4) operation as a control variable of multi-cascaded PLs. And we also present new PL synthesis algorithms to synthesize QGFSOP expressed 24 (1-qudit) functions by applying three PL operators as ab(mutual permutation), + D(addition), and XA (multiplication). Finally architectures, circuits, and a CMOS implementation to realize proposed PL synthesis algorithms for $Ax^C$+D(GF4) functions are presented.

키워드

참고문헌

  1. Mozammel H. A. Khan and Marek A. Perkowski, "GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits," Proc. of 37th IEEE Int, Symp. on Multiple-Valued Logie(ISMVL 2007). May 13 - May 16. Norway, Oslo, pp. 11-16, 2007.
  2. Mozammel H. A. Khan, Nafisa K. Siddika, and Marek A. Perkowski, "Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function using Quaternary Galois Field Decision Diagram," Proc. of 38th IEEE Int. Symp. on Multiple-Valued Logic (ISMVL 2008), pp.125-130. 2008.
  3. Ricardo Cunha, Henri Boudinov, and Luigi Carro, "Quaternary Look-up Tables Using Voltage-Mode CMOS Logic Design," Proc. of 37th IEEE Int. Symp. on Multlple-Valued Logie(ISMVL 2007), May 13 - May 16, Norway. Oslo. pp.56-61, 2007.
  4. F.J. Pelayo, A. Prieto, A. Lloris, and J. Ortega, "CMOS Current-Mode Multivalued PLA's," IEEE Tran. on Circuits and Systems, vol.38, no.4, pp. 434-441, April 1991. https://doi.org/10.1109/31.75400
  5. Carlos Roberto Mingoto Junior, "A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistor," Proc. of 36th IEEE Int. Symp. on Multiple-Valued Lagic(ISMVL 2006), pp.15-20, 2006.
  6. Nobuaki Okada and Michitaka Kameyama, "Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits," Proc. of 37th IEEE Int. Symp. on Multiple-Valued Logic(ISMVL 2007), May 13 - May 16, Norway. Oslo, pp.25-30, 2007.
  7. Nabil Abu - Khader and Pepe Siy, "Inverion/Division in Galois Field Using Multiple-Valued Logic." Proc. of 37th IEEE Int. Symp. on Multiple-Valued Logic(ISMVL 2007), May 13 - May 16, Norway, Oslo. pp,17-22. 2007.