References
- K. Yim, "A novel memory hierarchy for flash memory based storage systems," IEEK J. Semiconductor Technology and Science, vol.5, no.4, pp.262-269, Dec. 2005.
- K. Takeuchi, "Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30nm low-power high-speed solid-state drives (SSD)," IEEE J. Solid-State Circuits, vol.44, no.4, pp.1227-1234, Apr. 2009. https://doi.org/10.1109/JSSC.2009.2014027
- C. Lee, S. Baek, and K. Park, "A hybrid flash file system based on NOR and NAND flash memories for embedded devices," IEEE Trans. on Computers, vol.57, no.7, pp.1002-1008, Jul. 2008. https://doi.org/10.1109/TC.2008.14
- Y. Maeda, H. Kaneko, "Error control coding for multilevel cell flash memories using nonbinary low-density parity-check codes," in Proc. ISDFT in VLSI Systems, pp.367-375, 2009.
- 김영일, 이학수, 김태원, 김동현, 윤한섭, 곽계달, "빠른 MLC(Multi-Level Cell) 프로그램 속도를 위한 ISPP(Incremental Step Pulse Program) 알고리즘 및 회로," 대한전자공학회 하계종합학술대회, pp.530-531, 2009.
- 이수관, 민상렬, 조유근, "플래시 메모리 관련 최근 기술 동향," 정보과학회지, no.24, vol.12, pp.99-106, Dec. 2006.
- T.K. Kim, S.N. Chang, and J.H. Choi, "Floating gate technology for high performance 8-level 3-bit NAND flash memory," Elsevier Solid-State Electronics, vol.53, no.7, pp.792-797, July 2009. https://doi.org/10.1016/j.sse.2009.03.019
- A. Ghetti, L. Bortesi, and L. Vendrame, "3D simulation study of gate coupling and gate crossinterference in advanced floating gate non-volatile memories," Elsevier Solid-State Electronics, vol.49, no.11, pp.1805-1812, Nov. 2005. https://doi.org/10.1016/j.sse.2005.10.014
- H. Liu, S. Groothuis, C. Mouli, J. Li, K. Parat, and T. Krishnamohan, "3D simulation study of cell-cell interference in advanced NAND flash memory," in Proc. WMED, pp.1-3, 2009.
- J.D. Lee, S.H. Hur, and J.D. Choi, "Effects of floating-gate interference on NAND flash memory cell operation," IEEE Electron Deivce Letters, vol.23, no.5, pp.264-266, May 2002. https://doi.org/10.1109/55.998871
- J. Postel-Pellerin, F. Lalande, P. Canet, R. Bouchakour, F. Jeuland, B. Bertello, and B. Villard, "Extraction of 3D parasitic capacitances in 90nm and 22nm NAND flash memories," Elsevier Micro electronics Reliability, vol.49, no.9, pp.1056-059, July 2009. https://doi.org/10.1016/j.microrel.2009.06.020
- T.H. Cho, Y.T. Lee, E.C. Kim, J.W. Lee, S.M. Choi, S.J. Lee, D.H. Kim, W.G. Han, Y.H. Lim, J.D. Lee, J.D. Choi, and K.D. Suh, "A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes," IEEE J. Solid-State Circuits, vol.36, no.11, pp.1700-1706, Nov. 2001. https://doi.org/10.1109/4.962291
- M.C Park, K.S. Kim, J.H. Park, and J.H. Choi, "Direct field effect of neighboring cell transistor on cell-to-cell interference of NAND flash cell arrays," IEEE Electron Device Letters, vol.30, no.2, pp.174-177, Feb. 2009. https://doi.org/10.1109/LED.2008.2009555
- S.G. Jung, K.W. Lee, K.S. Kim, S.W. Shin, S.S. Lee, J.C. Om, G.H. Bae, and J.H. Lee, "Modeling of VTH shift in NAND flash-memory cell device considering crosstalk and short-channel effects," IEEE Trans. on Electron Devices, vol.55, no.4, pp.1020-1026, April 2008. https://doi.org/10.1109/TED.2008.916769
- K.T. Park, M.G. Kang, D.G. Kim, S.W. Hwang, B.Y. Choi, Y.T. Lee, C.H. Kim, and K.N. Kim, "A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories," IEEE J. Solid-State Circuits, vol.43, no.4, pp.919-928, April 2008. https://doi.org/10.1109/JSSC.2008.917558
- C.H. Lee, S.K. Lee, S.H. Ahn, J.H. Lee, W.S. Park, Y.D. Cho, C.K. Jang, C.W. Yang, S.H. Chung, I.S. Yun, B.G. Joo, B.K. Jeong, J.Y. Kim, J.K. Kwon, H.J. Jin, Y.J. Noh, J.Y. Ha, M.S. Sung, D.I. Choi, S.H. Kim, J.W. Choi, T.H. Jeon, J.S. Yang, and Y.H. Koh, "A 32Gb MLC NAND-flash memory with Vthendurance-enhancing schemes in 32nm CMOS," in Proc. ISSCC, pp.446-447, 2010.
- T. H. Cho, Y. T. Lee, E. C. Kim, J. W. Lee, S. M. Choi, S. J. Lee, D. H. Kim, W. K. Han, Y. H. Lim, J. D. Lee, J. D. Choi, and K. D. Suh "A 3.3V 1Gb multi-level NAND flash memory with non-uniform threshold voltage distribution," in Proc. ISSCC, pp.28-29, 2001.