JSTS:Journal of Semiconductor Technology and Science

  • 제9권3호
  • /
  • Pages.166-173
  • /
  • 2009
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

Reliability Characteristics of La-doped High-k/Metal Gate nMOSFETs

  • Kang, C.Y. (SEMATECH) ;
  • Choi, R. (Inha University) ;
  • Lee, B.H. (Dept. of Nanobio Materials Electronics and Dept. of Materials Science and Engineering, Gwangju Institute of Science and Technology) ;
  • Jammy, R. (SEMATECH)
  • 발행 : 2009.09.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.

키워드

참고문헌

  1. K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Rarade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45nm logic techno-logy with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging," in Technical Digest - International Electron Devices Meeting, IEDM, 2007, pp. 247-250
  2. M. T. Bohr, R. S. Chau, T. Ghani, and K. Mistry, 'The high-k solution," IEEE Spectrum, Vol. 44, pp. 29-35, 2007 https://doi.org/10.1109/MSPEC.2007.4337663
  3. B. H. Lee, C. D. Young, R. Choi, J. H. Sim, G. Bersuker, C. Y. Kang, R. Harris, G. A. Brown, K. Matthews, and S. C. Song, "Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)," Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 859-862, 2004
  4. C. Y. Kang, R. Choi, J. H. Sim, C. Young, B. H. Lee, G. Bersuker, and J. C. Lee, "Charge trapping effects in HfSiON dielectrics on the ring oscillator circuit and the single stage inverter operation," in Technical Digest - International Electron Devices Meeting, IEDM, San Francisco, CA, 2004, pp. 485-488
  5. C. D. Young, G. Bersuker, D. Heh, A. Neugroschel, R. Choi, C. Y. Kang, J. Tun, and B. H. Lee, "Electrical characterization methodologies for the assessment of high-? gate dielectric stacks," in ECS Transactions, Washington, DC, 2007, pp. 335-346
  6. A. Kerber, E. Cartier, R. Degraeve, P. J. Roussel, L. Pantisano, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, "Charge trapping and dielectric reliability of SiO2-Al2O3 gate stacks with TiN electrodes," IEEE Transactions on Electron Devices, Vol. 50, pp. 1261-1269, 2003 https://doi.org/10.1109/TED.2003.813486
  7. J. Lee, H. Park, H. Choi, M. Hasan, M. Jo, M. Chang, B. H. Lee, C. S. Park, C. Y. Kang, and H. Hwang, "Modulation of TiSiN effective work function using high-pressure postmetallization annea-ling in dilute oxygen ambient," Applied Physics Letters, Vol. 92, 2008
  8. S. C. Song, Z. B. Zhang, M. M. Hussain, C. Huffman, J. Barnett, S. H. Bae, H. J. Li, P. Majhi, C. S. Park, and B. S. Ju, "Highly manufacturable 45 nm LSTP CMOSFETs using novel dual high-k and dual metal gate CMOS integration," VLSI Symp. Tech. Dig, 2006
  9. S. Abermann, J. Efavi, G. Sjöblom, M. Lemme, J. Olsson, and E. Bertagnolli, "Impact of Al-, Ni-, TiN-, and Mo-metal gates on MOCVD-grown HfO2 and ZrO2 high-k dielectrics," Microelectronics Reliability, Vol. 47, pp. 536-539, 2007 https://doi.org/10.1016/j.microrel.2007.01.002
  10. Y. H. Kim, R. Choi, R. Jha, J. H. Lee, V. Misra, and J. C. Lee, "Effects of barrier height ($\phi$B) and the nature of Bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology," in Digest of Technical Papers - Symposium on VLSI Technology, 2004, pp.138-139
  11. Y. T. Hou, T. Low, B. Xu, M. F. Li, G. Samudra, and D. L. Kwong, "Impact of metal gate work function on nano CMOS device performance," in International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, 2004, pp. 57-60
  12. M. M. Hussain, C. Smith, P. Kalra, J. W. Yang, G. Gebara, B. Sassman, P. Kirsch, P. Majhi, S. C. Song, R. Harris, H. H. Tseng, and R. Jammy, "Dual work function high-k/metal gate CMOS FinFETs," in ESSDERC 2007 - Proceedings of the 37th Euro-pean Solid-State Device Research Conference, 2008, pp. 207-209
  13. C. Y. Ren, H. Y. Kang, J. F. Wang, X. P. Ma, H. Chan, D. S. H. Li, and M. F. Kwong, "A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/by using HfN replacement gate," Electron Device Letters, IEEE, Vol. 25, pp. 580-582, 2004 https://doi.org/10.1109/LED.2004.832535
  14. P. D. Kirsch, M. A. Quevedo-Lopez, S. A. Krishnan, C. Krug, H. AlShareef, C. S. Park, R. Harris, N. Moumen, A. Neugroschel, and G. Bersuker, "Band Edge n-MOSFETs with High-k/Metal Gate Stacks Scaled to EOT= 0.9 nm with Excellent Carrier Mobility and High Temperature Stability," Electron Devices Meeting, 2006. IEDM'06. International, pp. 1-4, 2006
  15. P. D. Kirsch, P. Sivasubramani, J. Huang, C. D. Young, M. A. Quevedo-Lopez, H. C. Wen, H. Alshareef, K. Choi, C. S. Park, K. Freeman, M. M. Hussain, G. Bersuker, H. R. Harris, P. Majhi, R. Choi, P. Lysaght, B. H. Lee, H. H. Tseng, R. Jammy, T. S. Boscke, D. J. Lichtenwalner, J. S. Jur, and A. I. Kingon, "Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning," Applied Physics Letters, Vol. 92, p. 092901, 2008 https://doi.org/10.1063/1.2890056
  16. P. Sivasubramani, T. S. Böscke, J. Huang, C. D. Young, P. D. Kirsch, S. A. Krishnan, M. A. Quevedo-Lopez, S. Govindarajan, B. S. Ju, H. R. Harris, D. J. Lichtenwalner, J. S. Jur, A. I. Kingon, J. Kim, B. E. Gnade, R. M. Wallace, G. Bersuker, B. H. Lee, and R. Jammy, "Dipole moment model explaining nFET vt tuning utilizing La. Sc, Er, and Sr doped HfSiON dielectrics," in Digest of Tech-nical Papers - Symposium on VLSI Technology, 2007, pp. 68-69
  17. X. P. Wang, L. Ming-Fu, C. Ren, X. F. Yu, C. Shen, H. H. Ma, A. Chin, C. X. Zhu, N. Jiang, M. B. Yu, and K. Dim-Lee, "Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs,' Electron Device Letters, IEEE, vol. 27, pp. 31-33, 2006 https://doi.org/10.1109/LED.2005.859950
  18. Y. Yamamoto, K. Kita, K. Kyuno, and A. Toriumi, "Study of La-induced flat band voltage shift in metal/HfLaO x/SiO2/Si capacitors," Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 46, pp. 7251-7255, 2007 https://doi.org/10.1143/JJAP.46.7251
  19. Y. Abe, N. Miyata, Y. Shiraki, and T. Yasuda, "Dipole formation at direct-contact Hf O2 Si interface," Applied Physics Letters, Vol. 90, 2007
  20. B. J. O. Sullivan, R. Mitsuhashi, G. Pourtois, M. Aoulaiche, M. Houssa, N. V. d. Heyden, T. Schram, Y. Harada, G. Groeseneken, P. Absil, S. Biesemans, T. Nakabayashi, A. Ikeda, and M. Niwa, "Reliability study of La[sub 2]O[sub 3] capped HfSiON high-permittivity n-type metal-oxide-semiconductor field-effect transistor devices with tantalum-rich electrodes," Journal of Applied Physics, Vol. 104, p. 044512, 2008 https://doi.org/10.1063/1.2967819
  21. B. H. Lee, C. Y. Kang, T. H. Lee, J. Barnett, R. Choi, S. C. Song, and R. Jammy, "Reliability of thich oxides integrated with HfSiO~ x gate dielec-tric," SOLID STATE DEVICES AND MATERIALS, Vol. 2006, p. 1122, 2006
  22. K. Okada, H. Ota, W. Mizubayashi, H. Satake, A. Ogawa, K. Iwamoto, T. Horikawa, T. Nabatame, and A. Toriumi, "Quantitative analysis of contribution of initial traps to breakdown in HfAlOx/SiO2 stacked gate dielectrics," in Digest of Technical Papers - Symposium on VLSI Technology, 2005, pp. 166-167
  23. K. Okada, H. Ota, T. Nabatame, and A. Toriumi, "Dielectric breakdown in high-K gate dielectrics - Mechanism and lifetime assessment," in Annual Proceedings - Reliability Physics (Symposium), 2007, pp. 36-43
  24. G. Ribes, S. Bruye?re, M. Denais, F. Monsieur, D. Roy, E. Vincent, and Ghibaudo, "High-k dielectrics breakdown accurate lifetime assessment metho-dology," in IEEE International Reliability Physics Symposium Proceedings, 2005, pp. 61-66
  25. G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, "Review on high-k dielectrics reliability issues," IEEE Transactions on Device and Materials Reliability, Vol. 5, pp. 5-19, 2005 https://doi.org/10.1109/TDMR.2005.845236
  26. J. H. Sim, B. H. Lee, R. Choi, S. C. Song, and G. Bersuker, "Hot carrier degradation of HfSiON gate dielectrics with TiN electrode," IEEE Transactions on Device and Materials Reliability, Vol. 5, pp. 177-182, 2005 https://doi.org/10.1109/TDMR.2005.851211
  27. S. Zafar, A. Kumar, E. Gusev, and E. Cartier, 'Threshold voltage instabilities in high-? gate dielectric stacks," IEEE Transactions on Device and Materials Reliability, Vol. 5, pp. 45-64, 2005 https://doi.org/10.1109/TDMR.2005.845880
  28. A. Neugroschel, G. Bersuker, R. Choi, C. Cochrane, P. Lenahan, D. Heh, C. Young, C. Y. Kang, B. H. Lee, and R. Jammy, "An accurate lifetime analysis methodology incorporating governing NBTI me-chanisms in high-k/SiO2 gate stacks," in Technical Digest - International Electron Devices Meeting, IEDM, 2006
  29. G. Bersuker, J. H. Sim, C. S. Park, C. D. Young, S. Nadkarni, R. Choi, and B. H. Lee, "Intrinsic Threshold Voltage Instability of the HFO2 NMOS Transistors," Reliability Physics Symposium Procee-dings, 2006. 44th Annual., IEEE International, pp. 179-183, 2006 https://doi.org/10.1109/RELPHY.2006.251213
  30. E. M. Vogel, K. Z. Ahmed, B. Hornung, W. K. Henson, P. K. McLarty, G. Lucovsky, J. R. Hauser, and J. J. Wortman, "Modeled tunnel currents for high dielectric constant dielectrics," IEEE Transac-tions on Electron Devices, Vol. 45, pp. 1350-1355, 1998 https://doi.org/10.1109/16.678572
  31. C. Y. Kang, C. S. Park, D. Heh, C. Young, P. Kirsch, H. B. Park, R. Choi, G. Bersuker, J. W. Yang, B. H. Lee, J. Lichtenwalner, J. S. Jur, A. I. Kingon, and R. Jammy, "Performance and reliability characteristics of the band edge high-k/metal gate nMOSFETs with La-doped Hf-silicate gate dielec-trics," in IEEE International Reliability Physics Symposium Proceedings, 2008, pp. 663-664
  32. C. Y. Kang, C. D. Young, J. Huang, P. Kirsch, D. Heh, P. Sivasubramani, H. K. Park, B. G, B. H. Lee, H.S. Choi, K.T. Lee, Y-H. Jeong, J. Lichtenwalner, A. I. Kingon, H-H Tseng, and R. Jammy, "The Impact of La-doping on the Reliability of Low Vth High-k/Metal Gate nMOSFETs under Various Gate Stress Conditions," in Technical Digest – Interna-tional Electron Devices Meeting, 2008, pp. p.115-118

피인용 문헌

  1. Effects of Small Geometries on the Performance of Gate First High- $\kappa$ Metal Gate NMOS Transistors vol.59, pp.10, 2012, https://doi.org/10.1109/TED.2012.2208647