대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Stacked Interleaved 방식의 50MHz 스위칭 주파수의 벅 변환기

Stacked Interleaved Buck DC-DC Converter With 50MHz Switching Frequency

  • 김영재 (한양대학교 전자컴퓨터공학) ;
  • 남현석 (한양대학교 전자컴퓨터공학) ;
  • 안영국 (한양대학교 전자컴퓨터공학) ;
  • 노정진 (한양대학교 전자컴퓨터공학)
  • Kim, Young-Jae (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Nam, Hyun-Seok (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Ahn, Young-Kook (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.) ;
  • Roh, Jeong-Jin (Dep. of Electronic, Electrical, Control and Instrumentation Engineering, Hanyang Univ.)
  • 발행 : 2009.06.25
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초록

본 논문에서는 인덕터와 커패시터를 집적화한 DC-DC 벅 변환기를 설계하였다. 출력전압의 리플크기를 줄이기 위해 stacked interleaved 방식을 이용하였고 변환기의 제어부는 전압모드 방식의 제어방법을 사용하여 설계하였다. 설계한 DC-DC 벅 변환기는 표준 $0.5{\mu}m$ CMOS 공정으로 제작 중이며 전체면적은 $9mm^2$이다. 설계된 회로는 $3V{\sim}5V$의 입력전압에서 동작하며 LC 필터의 크기를 줄이기 위해 50MHz의 주파수로 동작하였다. 최대 250mA의 부하전류 구동이 가능하며 최대 71%의 전력변환 효율을 가졌다.

In this paper, DC-DC buck converter with on-chip filter inductor and capacitor is presented. By operating at high switching frequency of 50MHz with stacked interleaved topology, we reduced inductor and capacitor sizes compared to previously published DC-DC buck converters. The proposed circuit is designed in a standard $0.5{\mu}m$ CMOS process, and chip area is $9mm^2$. This circuit operated at the input voltage of $3{\sim}5V$ range, the maximum load current of 250mA, and the maximum efficiency of 71%.

키워드

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