References
- P. Vuillod, L. Benini, A.Bogliolo, and G. De Micheli, "Clock-skew optimization for peak current reducetion," in Proceedings of ISLPED, pp. 265-270, 1996
- W.-C. D. Lam, C.-K. Koh, and C.-W. A. Tsao, "Power supply noise suppression via clock skew scheduling", in Proceedings of ISQED, pp. 355-360, 2002 https://doi.org/10.1109/ISQED.2002.996772
- W.-C. D. Lam, C.-K. Koh, and C.-W. A. Tsao, "Clock scheduling for power supply noise suppression using genetic algorithm with selective gene therapy," in Proceedings of ISQED, pp. 327-332, 2003 https://doi.org/10.1109/ISQED.2003.1194753
- A. Mukherjee and R. Sankaranarayan, "Retiming and clock scheduling to minimize simultaneous switching," in Proceedings of IEEE SOCC, pp. 259-262, 2004
- N. Shenoy, R. K. Brayton, and A. L. Sangiovanni- Vincentelli, "Graph algorithms for clock schedule optimization," in Proceedings of ICCAD, pp.132- 136, 1992
- X. Wang, J. Shi, Y. Cai. and X. Hong, "Heuristic power/ground network and floorplan codesign method," in Proceedings of ASPDAC, pp. 617-622, 2008
- T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise," in Proceedings of ISPD, pp.160-167, 2008
- D.E. Khalil, and Y. Ismail, "Optimum sizing of power grids for IR drop," in Proceedings of ISCAS, pp. 481-484, 2006
- H.-M. Chen, L.-D. Huang, and M. D. F. Wong, "Simultaneous power supply planning and noise avoidance in floorplan design,”" IEEE Transactions on CAD, vol. 24, no. 4, pp. 578-587, Apr. 2005
- S. Zhao, K. Roy, and C.-K. Koh, "Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning," IEEE Transactions on CAD, vol. 21, no. 1, pp. 81-92, Jan. 2002 https://doi.org/10.1109/43.974140
- Nangate 45nm Open Cell Library: http://www.si2. org/openeda.si2.org/projects/nangatelib/
- "Liberty Reference Manual (Version 2006.06)," Synopsys, 2006
- "Library Compiler Reference Manual, Volume 1," Synopsys, 1999
- S. Kirkpatrick, C. D. Gelatt Jr., and M. P. Vecchi, "Optimization by simulated annealing," Science, May 1983
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