대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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MIMO-OFDM 기반 SDR 시스템을 위한 효율적인 FFT 프로세서 설계

Design of Efficient FFT Processor for MIMO-OFDM Based SDR Systems

  • 발행 : 2009.12.25
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 MIMO-OFDM 기반의 SDR 시스템을 위한 효율적인 FFT 구조를 제안한다. 제안한 scalable FFT/IFFT 프로세서는 64/128/512/1024/2048-point FFT 연산을 가변적으로 수행할 수 있다. 또한 mixed radix (MR) 기법과 multi-path delay commutator (MDC) 구조를 사용하여 비단순 승산을 줄임으로써 기존의 설계 구조에 비해 시스템 수율 변화 없이 하드웨어 복잡도를 크게 감소시켰다. 제안된 scalable FFT/IFFT 프로세서는 하드웨어 설계 언어 (HDL)를 이용하여 설계 되었고, 0.18um CMOS 스탠다드 셀 라이브러리를 이용하여 논리 합성되었다. 논리합성 결과 4채널 radix-2 single-path delay feed back (R2SDF) FFT 프로세서와 비교시 59% 감소된 게이트 수와 39% 감소된 메모리로 구현 가능함을 확인하였고, 4채널 radix-2 MDC (R2MDC) FFT 프로세서와 비교시 16.4% 감소된 게이트 수와 26.8% 감소된 메모리로 구현 가능함을 확인하였다.

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

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참고문헌

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