The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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A Novel Current Steering Cell Matrix DAC Architecture with Reduced Decoder Area

디코더 면적을 줄이는 새로운 전류구동 셀 매트릭스 DAC 구조

  • 정상훈 (전북대학교 공과대학 전자정보공학부) ;
  • 신홍규 (원광대학교 공과대학 전기전자및정보공학부) ;
  • 조성익 (전북대학교 공과대학 전자정보공학부)
  • Published : 2009.03.01
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Abstract

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.

Keywords

References

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