Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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High Performance Nand Flash Controller using Multi-Processing Scheme

고속 처리가 가능한 다중처리 Nand 플래시 Controller

  • Kang, Shin-Wook (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Lee, Dong-Woo (Digital Media R&D Center, Samsung Electronic Co., Ltd.) ;
  • Jeong, Seong-Hun (Digital Media R&D Center, Samsung Electronic Co., Ltd.) ;
  • Lee, Yong-Surk (Department of Electrical and Electronic Engineering, Yonsei University)
  • 강신욱 (연세대학교 전기전자공학과) ;
  • 이동우 (삼성전자 DM연구소) ;
  • 정성훈 (삼성전자 DM연구소) ;
  • 이용석 (연세대학교 전기전자공학과)
  • Published : 2009.01.25
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Abstract

Lately, NAND flash cards have been used to store massive amounts of multimedia data. However, these nand flash cells itself has a slow operation time and by that, the nand flash cards are not appropriate for high performance massive data transfer. Indeed, most flash card products have a disadvantage in that they require plenty of time to transfer massive amounts of data. Therefore, we propose a new architectural design for the hardware and software of the NAND flash cards by improving their data transfer rate. Our design is based on a multiprocessing which is different from the conventional serial processing method. We simulated our design under the VIP (Virtual IP) environment, and verified our work using FPGA test platforms. As a result, the downloading performances was approximately 160MB/s on VIP and 85.3MB/s on FPGA.

NAND 플래시 메모리를 이용한 카드가 보편화되어 이제는 대량의 멀티미디어 데이터를 모두 저장할 수 있는 수준에 이르렀다. 하지만 NAND 플래시 셀(cell)의 느린 동작으로 인하여 대량의 데이터를 빠르게 전송하기에는 많이 부족한 수준이다. 즉 대량의 멀티미디어 데이터를 NAND 플래시 메모리 카드로 전송할 경우 많은 시간이 걸리는 단점이 있다. 이에 본 논문에서는 데이터 전송률을 높이기 위한 새로운 하드웨어 및 소프트웨어의 구조를 제안한다. 제안하는 구조에서는 기존의 직렬 처리(serial processing) 기법과 다른, 다중 처리(multiprocessing) 기법을 사용하였다. 제안된 구조를 이용하여 VIP(Virtual IP) 환경에서 시뮬레이션하고 FPGA 보드환경에서 최종 실험하였다. 실험 결과 VIP환경에서는 160MB/s의 다운로드 성능을 볼 수 있었으며, FPGA 보드환경에서는 85.3MB/s의 다운로드 성능을 볼 수 있었다.

Keywords

References

  1. Mauricio Alvarez, Esther Salam'1, Alex Ramirez, Mateo Valero, 'A Perfonnance Characterization of High Definition Digital Video Decoding using H.2641 A VC', Workload Characterization Symposium, 2005. Proceedings of the IEEE International, pp. 24-33, Oct 2005
  2. http://www.sandisk.com/Products/Catalog(119J)-SanDisk_ExtremeJV _ Compactflashaspx
  3. www.usb.org
  4. PCI Express Base Specification 2.0
  5. www.sata-io.org
  6. Samsung Electronic Co., Ltd, SLC NAND Flash Memory Data Sheet, http:;/www.samsung.com
  7. Micron Technology, Inc., SLC NAND flash memory data Sheet, http://www.micron.com
  8. Lexar Media, Inc., 'Non-volatile Memory control', US Patent, no. 7,215,580 8 May 2007
  9. Horii, Takashi Yoshida, Keiichi Nozoe, Atsushi, 'Memory system and Memory card', US Patent, no. 7,290,109, 2007
  10. ONFCWhitePaper.pdf, http://www.onfi.org
  11. Chansik Park, Prakash Talawar, Daesik Won, Myungjin Jung, JungBeen Im, Suksan Kim, Y oungjoon Choi, 'A High Performance NAND Flash Controller for NAND Flash-based Solid State Disk', Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st, pp, 17-20, 2006
  12. Schuetz, R. HakJune Oh, Jin-Ki Kim Hong-Beom Pyron, Przybylski, SA, Gillingham, P. 'HyperLink NAND flash Architecture for Mass Storage Applications', Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE, pp, 3-4, Aug 2007
  13. Mei-Ling Chiang, Paul C. H Lee, and Ruei-Chuan Chang, 'Managing Hash Memory in Personal Communication Devices, ' in Proceedings of the 1997 International Symposium on Consurrer Electronics (ISCE'97), pp, 177-182, 1997
  14. Intel Corporation, 'Understanding the flash translation layer (FIL) specification,' APPUCATlON NOTE (AP-684), http://developer.intel.com/
  15. Jesung Kim, Jong Min Kim, Nob, SH, Sang Lyul :Min, and Y ookun Cho, 'A space-efficient flash translation layer for Compact flash systems,' Consurrer Electronics, IEEE transactions on, vol. 48, no. 2, May 2002
  16. M-Systems, 'TrueFFS? Wear-Leveling Mechanisrn,', Technical Note (TN-DOC-017), May, 2002
  17. Dawoon Jung, Yoon-Hee Chae, Heeseung Jo, Jin-Soo Kim, and Joonwon Lee, 'A Group-Based Wear-Leveling Algorithm for Large--Gapacity flash rrermry storage Systems,' in Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems (CASES'07), pp, 160-164, 2007
  18. TFS4$^{TM}$ (transactional File System 4$^{TM}$), http://www.sconsung.com/global/business/semiconductor/products/flash/Products_flashSoftuware.html