전기학회논문지 (The Transactions of The Korean Institute of Electrical Engineers)

  • 제58권1호
  • /
  • Pages.107-112
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  • 2009
  • /
  • 1975-8359(pISSN)
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  • 2287-4364(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

디지털 방송 수신용 System in Package 설계 및 제작

Design and Fabrication of the System in Package for the Digital Broadcasting Receiver

  • 김지균 (명지대 공대 전기공학과) ;
  • 이헌용 (명지대 공대 전기공학과)
  • 발행 : 2009.01.01
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초록

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

키워드

참고문헌

  1. Christopher M. Scanlan and Nozad Karim, ''System-in-Package technology, application and trends'', SMTA International Proceedings, 2001, pp. 764-773
  2. 이성수, 'SiP(System-in Package) 기술', 주간기술동향, Vol. 242, pp. 25-33, 2006.4
  3. 윤종광, 'SOP(System-on-Packaging) for Mega-Function System Integration', 세라미스트, Vol. 8, No. 6, pp. 46-52, 2005. 12
  4. Andrew Holland, 'Innovations in QFN Packaging Targeting RF and Image Sensor System-in-Package', IMAPS MicroTech 2006
  5. Wei Koh, 'System in Package (SiP) Technology Applications', IEEE Electronic Packaging Technology Conference, pp. 61-66, 2005. 8 https://doi.org/10.1109/ICEPT.2005.1564753
  6. Shan Gao, Jupyo Hong 외 3인, 'Effects of Packaging Materials on the Reliability of System in Package', IEEE/ICEPT Electronic Packaging Technology Conference, pp. 1-5, 2007. 8 https://doi.org/10.1109/ICEPT.2007.4441427
  7. Tiao Zhou, Mark Gerber, Moody Dreiza, 'Stacked Die Package Design Guidelines', IMAPS 2004
  8. Priest, J., Ahmad, M.외 3인, 'Feasibility Study of a SiP for High Performance and Reliability Product Application', IEEE High Density Microsystem Design and Packaging and Component Failure Analysis Conference, pp. 1-5, 2005. 7 https://doi.org/10.1109/HDP.2005.251422
  9. M. Karnezos, F. Carson and R. Pendse, '3D packaging promises performance, reliablility gains with small footprints and lower profiles', Chip Scale Review, 2005
  10. N. Tanaka and Y. Yoshimira, 'Ultra-Thin 3D-Stacked SiP formed Using Room-Temperature Bonding between Stacked Chips', 2005 ECTC Conference, pp. 788-794, 2005