대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Short-gate SOI MESFET의 문턱 전압 표현 식 도출을 위한 해석적 모델

An Analytical Model for Deriving The Threshold Voltage Expression of A Short-gate Length SOI MESFET

  • 갈진하 (홍익대학교 전자전기공학부) ;
  • 서정하 (홍익대학교 전자전기공학부)
  • Kal, Jin-Ha (School of Electronic & Electrical Eng., Hongik Univ.) ;
  • Suh, Chung-Ha (School of Electronic & Electrical Eng., Hongik Univ.)
  • 발행 : 2008.07.25
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초록

본 논문에서는 short-gate SOI MESFET의 문턱전압 도출을 위한 간단한 해석적 모델을 제시하였다. 완전 공핍된 실리콘 채널 영역에서는 2차원 Poisson 방정식을, buried oxide 영역에서는 2차원 Laplace 방정식을 반복법(iteration method)을 이용해 풀어 각 영역 내에서의 전위 분포를 채널에 수직한 방향의 좌표에 대해 5차 다항식으로 표현하였으며 채널 바닥 전위를 구하였다. 채널 바닥 전위의 최소치가 0이 되는 게이트 전압을 문턱 전압으로 제안하여 closed-form의 문턱 전압 식을 도출하였다. 도출된 문턱 전압 표현 식을 모의 실험한 결과, 소자의 구조 parameter와 가해진 bias 전압에 대한 정확한 의존성을 확인할 수 있었다.

In this paper, a simple analytical model for deriving the threshold voltage of a short-gate SOI MESFET is suggested. Using the iteration method, the Poisson equation in the fully depleted silicon channel and the Laplace equation in the buried oxide region are solved two-dimensionally, Obtained potential distributions in each region are expressed in terms of fifth-order of $\chi$, where $\chi$ denotes the coordinate perpendicular to the silicon channel direction. From them, the bottom channel potential is used to describe the threshold voltage in a closed-form. Simulation results show the dependencies of the threshold voltage on the various device geometry parameters and applied bias voltages.

키워드

참고문헌

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