대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

루프 대역폭 조절기를 이용한 빠른 위상 고정 시간을 갖는 이중 루프 위상고정루프

A Fast Locking Dual-Loop PLL with Adaptive Bandwidth Scheme

  • 송윤귀 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 최영식 (부경대학교 전자컴퓨터정보통신공학부)
  • Song, Youn-Gui (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University) ;
  • Choi, Young-Shig (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University)
  • 발행 : 2008.05.25
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초록

본 논문에서는 루프 대역폭을 조절하여 빠른 위상 고정 시간을 갖는 새로운 구조의 이중 루프 위상고정루프를 제안하였다. 위상고정루프가 out-lock 상태일 때는 채널 간격의 1/10보다 더 큰 대역폭을 갖도록 하였으며, in-lock 부근에서는 채널 간격의 1/10 보다 더 작은 좁은 대역폭을 갖도록 하였다. 제안된 위상고정루프는 표준 CMOS $0.35{\mu}m$ 공정으로 HSPICE를 이용하여 설계 하였다. 시뮬레이션 결과 PLL의 대역폭을 200KHz 채널 간격 보다 14배 크게 하여 80MHz의 주파수를 변화시키는데 $50{\mu}s$의 빠른 위상고정 시간을 갖는 것으로 나타났다.

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

키워드

참고문헌

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