참고문헌
- J.D. Foley, A. V. Dam, S. K. Feiner and J. F. Hughes, Computer Graphics : Principles and Practice, 2nd edition, Addison Wesley, Chapter 18, 1997
- Dave Astle and Dave Durnil, Opicro OpenGL ES Game Development, PTR, 2004.
- Kris Gray, Microsoft DirectX9 Programmable Pipeline, Microsoft Press 2004
- IEEE, ANSI/IEEE Standard 754-1985: IEEE Standard for Binary Floating-Point Arithmetic, IEEE Press, 1985
- Rubinfield, L.P, "A proof of the modified Booth's algorithm for multiplication," IEEE Transaction on Computer, vol.24, no.10, pp.1010-1015. October 1975 https://doi.org/10.1109/T-C.1975.224112
- M. Rooda, "Method to reduce the sign bit extension in a multiplier that uses the modified booth algorithm," Electronics Letters, vol 22, no.20, pp.1014-1015. 25h September, 1986 https://doi.org/10.1049/el:19860693
- C. S. Wallace, "A suggestion for parallel multipliers," IEEE Trans. Electron. Computer, no. EC-13, pp.14-17, Feb, 1964
- Mark R. Santoro, Gary Bewick and Mark A. Horowitz, "Rounding Algorithms for IEEE Multipliers", IEEE 9th Symposium on Computer Arithmetic, pp.176-183. 1989
- Robert K. Yu and Gregory B. Zyner, "167 MHz Radix-4 Floating Point Multiplier", IEEE 12th Symposium on Computer Arithmetic, 1 pp.149-154. 1995
- V.G. Oklobdjija, etal, "An algorithm and novel design of leading zero detector: comparison with logic synthesis," IEEE Transactions on VLSI, vol.2, pp.124-128, March 1994 https://doi.org/10.1109/92.273153
- J. Cortadella and J. M. Liaberia, "Evaluation of A+B=K conditions without carry propagation", IEEE Transaction on Computers, vol. 41, no.11, pp.1484-1488, Nov. 1992 https://doi.org/10.1109/12.177318
- Neil Burgess, "The flagged prefix adder and its applications in integer Arithmetic," Journal of VLSI Signal Processing, vol 31, pp.263-271, 2002 https://doi.org/10.1023/A:1015421507166
-
G. Goto, A. Inoue, and T. Izawa, "A 4.1-ns Compact 54
$\times$ 54-b Multiplier Utilizing Sign-select Booth Encoders," IEEE JSSC, vol.32, no.11, pp.1676-1682, November, 1997. - Yuyun Liao and David B. Roberts, "A High- Performance and Low-Power 32-bit Multiply-Accumulator Unit with Single-Instruction-Multiple-Data (SIMD) Feature," IEEE JSSC, vol.37, no.7, pp.926-931, August, 2004