대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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100% ASK 수신기를 위한 13.56MHz RFID Tag용 클럭 복원회로 설계

Design of Clock Recovery circuit for 13.56MHz RFID Tags with 100% ASK Receiver

  • 김지곤 (충북대학교 전기전자컴퓨터공학부) ;
  • 이경일 (충북대학교 전기전자컴퓨터공학부) ;
  • 김현식 (충북대학교 전기전자컴퓨터공학부) ;
  • 김재환 (충북대학교 전기전자컴퓨터공학부) ;
  • 김효종 (충북대학교 전기전자컴퓨터공학부) ;
  • 김시호 (충북대학교 전기전자컴퓨터공학부)
  • Kim, Ji-Gon (School of Electrical & Computer Engineering, Chungbuk National University) ;
  • Yi, Kyeong-Il (School of Electrical & Computer Engineering, Chungbuk National University) ;
  • Kim, Hyun-Sik (School of Electrical & Computer Engineering, Chungbuk National University) ;
  • Kim, J.H. (School of Electrical & Computer Engineering, Chungbuk National University) ;
  • Kim, Hyo-Jong (School of Electrical & Computer Engineering, Chungbuk National University) ;
  • Kim, Shi-Ho (School of Electrical & Computer Engineering, Chungbuk National University)
  • 발행 : 2008.11.25
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초록

ASK 100% RF 입력신호를 이용하는 13.56MHz RFID 태그를 위한 클럭 복원회로를 제안하였다. 제안한 클럭 복원회로는, 레지스터로 조절되는 DLL을 이용하여 입력 RF 신호의 크기가 0인 구간에서도 기준 클럭 신호를 사용하지 클럭을 생성하도록 설계되었다. 제안한 회로는 TSMC 0.18um 1P6M 공정을 사용하여 설계하였으며, 제안된 회로는 DLL의 위상 잠김 시간이 6.4usec 이하이며 공급전압이 3.3V에서 43uW를 소모한다.

We have proposed a clock recovery circuit for 13.56MHz RFID Tags using 100%, ASK RF input signal. The proposed clock recovery circuit generates clock pulses without reference clock by adapting register controlled DLL. The proposed circuit have designed by using a TSMC 0.18um 1P6M CMOS technology. The simulated results show that the phase locking time of the proposed circuit is about 6.4 usec and power consumption is about 43uW at supply voltage of 3.3V.

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참고문헌

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  2. KS X ISO/IEC 15693-1, Mar. 2003
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