전기학회논문지 (The Transactions of The Korean Institute of Electrical Engineers)

  • 제57권3호
  • /
  • Pages.488-493
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  • 2008
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  • 1975-8359(pISSN)
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  • 2287-4364(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

듀얼 모드형 고신뢰 PLC 모뎀 칩 설계 및 구현

Design and Implementation of the Dual-Mode Type Reliable PLC Modem Chip

  • 발행 : 2008.03.01
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초록

This paper represents a dual-mode type transmission technique for a high reliable narrow-band power line communication(PLC) modem, and its design and implementation of a system-on-chip(SoC). The proposed transmission technique is based on a Chirp modulation for the purpose of overcoming time variations of power line channel environments in the narrow-bandwidth of the frequency range of 95-145.5 kHz. The designed modem is fabricated utilizing a mixed 0.18 ${\mu}m$ CMOS technology. Especially, according to the power line channel environments the data transmission rate can be selectively changed into 2.5 kbps and 480 bps. The total hardware complexity of the implemented chip is about 50,000 gates, the power consumption is about 26mW, and the operating frequency is up to 5.12 MHz.

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참고문헌

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