WCDMA 통신용 I-Q 채널 12비트 1GS/s CMOS DAC

I-Q Channel 12bit 1GS/s CMOS DAC for WCDMA

  • Seo, Sung-Uk (Dept. of Electronic Engineering, Inha University) ;
  • Shin, Sun-Hwa (Dept. of Electronic Engineering, Inha University) ;
  • Joo, Chan-Yang (Dept. of Electronic Engineering, Inha University) ;
  • Kim, Soo-Jae (Dept. of Electronic Engineering, Inha University) ;
  • Yoon, Kwang-S. (Dept. of Electronic Engineering, Inha University)
  • 발행 : 2008.01.25

초록

본 논문에서는 WCDMA 통신용 송신기에 적용 가능한 12비트 1GS/s 전류구동 방식의 혼합형 DAC를 설계하였다. 제안된 DAC는 혼합형 구조로써 하위 4비트는 이진 가중치 구조, 중간비트와 상위비트는 4비트 온도계 디코더 구조로 12비트를 구성하였다. 제안된 DAC는 혼합형 구조에서 발생되는 지연시간에 따른 성능 저하를 개선하기 위해 지연시간보정 회로를 사용하였다. 지연시간보정 회로는 위상주파수 검출기, 전하펌프, 제어회로로 구성되어 이진 가중치 구조와 온도계 디코더 구조에서 발생하는 지연시간을 감소시킨다. 제안한 DAC는 CMOS $0.18{\mu}m$ 1-poly 6-metal n-well 공정을 사용하여 제작되었고 측정된 INL/DNL은 ${\pm}0.93LS/$ 0.62LSB 이하로 나타났다. 입력 주파수 1MHz에서 SFDR은 약 60dB로 측정되었고 SNDR은 51dB로 측정되었다. 단일 DAC의 전력소모는 46.2mW로 나타났다.

This paper describes a 12 bit 1GS/s current mode segmented DAC for WCDMA communication. The proposed circuit in this paper employes segmented structure which consists of 4bit binary weighted structure in the LSB and 4bit thermometer decoder structure in the mSB and MSB. The proposed DAC uses delay time compensation circuits in order to suppress performance decline by delay time in segmented structure. The delay time compensation circuit comprises of phase frequency detector, charge pump, and control circuits, so that suppress delay time by binary weighted structure and thermometer decoder structure. The proposed DAC uses CMOS $0.18{\mu}m$ 1-poly 6-metal n-well process, and measured INL/DNL are below ${\pm}0.93LSB/{\pm}0.62LSB$. SFDR is approximately 60dB and SNDR is 51dB at 1MHz input frequency. Single DAC's power consumption is 46.2mW.

키워드

참고문헌

  1. 이진성, 유형준, 'ICU WCDMA UE Radio Transceiver Implementation-Part I: Receiver performance analysis,' SoC R&D, pp. 16-21, Jun, 2005
  2. 이진성, 유형준, 'ICU WCDMA UE Radio Transceiver Iplementation-Part II: Transmitter performance analysis,' SoC R&D, pp. 25-29, Jul, 2005
  3. A. Van den Bosch, Marc A. F. Borrenmans, M. Steyaert and W. Sansen, 'A 10bit 1GSample/s Nyquist Current Steering CMOS D/A Converter,' IEEE J. Solid-State Circuits, vol. 36, No. 3, pp. 315-324, Mar. 2001 https://doi.org/10.1109/4.910469
  4. A. van den Bosch, M. Steyaert and W. Sansen, 'SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters,' Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on, vol. 3, No. 3, pp. 1193-1196, Sep. 1999
  5. Jurgen Deveugele and Michiel S.J.Steyaert, 'A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC,' IEEE J. Solid-State Circuits, vol. 41, No. 2, pp. 320-329 Feb. 2006 https://doi.org/10.1109/JSSC.2005.862342
  6. Kevin O'Sullivan, C. Gorman, M. Hennessy and Vincent Callaghan, 'A 12-bit 320-MSample/s Curret-Steering CMOS D/A Converter in 0.44mm2,' IEEE J. Solid-State Circuits, vol. 39, No. 7, pp. 1064-1072, July. 2004 https://doi.org/10.1109/JSSC.2004.829923
  7. Dongwon Seo, Gene H. AcAllister, 'A Low-Spurious Low-Power 12-bit 160MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter,' IEEE J. Solid-State Circuits, vol. 42, No. 3, pp. 486-495, Mar. 2007 https://doi.org/10.1109/JSSC.2006.891722
  8. Bernd Schaffer and Richard Adams, 'A 3V CMOS 400mW 14b 1.4GS/s DAC for Multi-Carrier Applications,' ISSCC, session 20, Feb. 2004
  9. John Hyde, Todd Humes, Chris Diorio, Mike Thomas, and Miguel Figueroa, 'A 300-MS/s 12-bit Digital-to-Analog Converter in Logic CMOS,' IEEE J. Solid-State Circuits, vol. 38, No. 5, pp. 734-740, May. 2003 https://doi.org/10.1109/JSSC.2003.810049
  10. Mike P. Tiilikainen, 'A 14-bit 1.8-V 20-mW 1mm2CMOSDAC,' IEEE J. Solid-State Circuits, vol. 36, No. 7, pp. 1144-1147, July. 2001 https://doi.org/10.1109/4.933474
  11. Yonghua Cong and Randall L. Geiger, 'A 1.5-V 14-Bit 100MS/s Self-Calibrated DAC,' IEEE J. Solid-State Circuits, vol. 38 No. 12, pp. 2051-2060, Dec. 2003 https://doi.org/10.1109/JSSC.2003.819163