ETRI Journal
- 제29권4호
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- Pages.463-469
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- 2007
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- 1225-6463(pISSN)
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- 2233-7326(eISSN)
A Phase-Locked Loop with Embedded Analog-to-Digital Converter for Digital Control
- Cha, Soo-Ho (Department of Electronics and Computer Engineering, Hanyang University) ;
- Jeong, Chun-Seok (Department of Electronics and Computer Engineering, Hanyang University) ;
- Yoo, Chang-Sik (Department of Electronics and Computer Engineering, Hanyang University)
- 투고 : 2006.08.10
- 발행 : 2007.08.31
초록
A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18