The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
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High Performance Coprocessor Architecture for Real-Time Dense Disparity Map

실시간 Dense Disparity Map 추출을 위한 고성능 가속기 구조 설계

  • 김정길 (연세대학교 컴퓨터과학과 BK21) ;
  • ;
  • 김신덕 (연세대학교 컴퓨터과학과)
  • Published : 2007.10.31
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Abstract

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.

본 논문에서는 위상기반 양안스테레오정합 알고리즘을 이용, 실시간으로 dense disparity map을 추출 가능한 고성능 가속기 구조를 설계하였다. 채택된 알고리즘은 웨이블릿 기반의 위상차 기법의 강건성과 위상상관 기법의 기본적인 control 기법을 결합한 Local Weighted Phase Correlation(LWPC) 스테레오정합 알고리즘으로서 4개의 주요 단계로 구성이 되어 있다. 해당 알고리즘의 효율적인 병렬 하드웨어의 설계를 위하여, 제안된 가속기는 각 단계의 기능블록은 SIMD(Single Instruction Multiple Data Stream) 모드로 동작하게 되며, 전체적으로 각 기능 블록은 파이프라인(pipeline) 모드로 실행된다. 그 결과 제안된 구조에서 제시된 파이프라인 동작 모드의 선형 배열 프로세서는 행렬 순차수행 방법에 의한 2차원 영상처리에서 전치메모리의 필요를 제거하면서도 연산의 일반성과 고효율을 유지하게 한다. 제안된 하드웨어 구조는 Xilinx HDL을 이용하여 필요한 하드웨어 자원을 look up table, flip flop, slice, memory의 소모량으로 표현하였으며, 그 결과 실시간 처리 성능의 단일 칩 구현 가능성을 보여주었다.

Keywords

References

  1. M. Z. Brown, D. Burschka, and G. D. Hager, 'Advances in computational stereo,' IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol. 25, Issue 8, pp.993-1008, Aug. 2003 https://doi.org/10.1109/TPAMI.2003.1217603
  2. H. Sunyoto, W. van der Mark, and D. M. Gavrila, 'A comparative study of fast dense stereo vision algorithms,' Proc. IEEE Intelligent Vehicles Symposium 2004, pp.319-324, 14-17 June 2004 https://doi.org/10.1109/IVS.2004.1336402
  3. T. Kanade, A. Yoshida, K. Oda, H. Kano, and M. Tanaka, 'A stereo machine for video-rate dense depth mapping and its new applications' Proc. IEEE CVPR '96, pp.196-202, 1966 https://doi.org/10.1109/CVPR.1996.517074
  4. Y. Goulermas and P. Liatsis, 'Feature-based stereo matching via coevolution of epipolar subproblems,' Proc. Seventh International Conference on Image Processing And Its Applications, Vol.1, pp.23-27, 13-15 July 1999 https://doi.org/10.1049/cp:19990274
  5. D. Fleet, A. Jepson, and M. Jenkin, 'Phase-based disparity measurement,' CVGIP: Image Understanding, Vol.53, pp. 198-210, 1991 https://doi.org/10.1016/1049-9660(91)90027-M
  6. D. J Fleet, 'Disparity from local weighted phasecorrelation,' Proc. Int. Conf. on Systems, Man, and Cybernetics, Vol.1, pp.48-54, 1994 https://doi.org/10.1109/ICSMC.1994.399810
  7. O. Faugeras, B. Hotz, H. Matthieu, T. Vieville, Z. Zhang, P. Fua, E. Theron, L. Moll, G. Berry, J Vuillemin, P. Bertin, and C. Proy, 'Real time correlation-based stereo: Algorithm, implementations and applications,' INRIA Technical Report 2013, 1993
  8. L. Matthies, A. Kelly, T. Litwin and G. Tharp, 'Obstacle Detection for Unmanned Ground Vehicles: A Progress Report,' Proc. Intelligent Vehicles '95 Symp., pp.66-71, 1995 https://doi.org/10.1109/IVS.1995.528259
  9. S. Kimura, T. Kanade, and H. Kano, A. Yoshida, E. Kawamura, and K. Oda, 'CMU Video-rate stereo machine,' Proc. Mobile Mapping Symp., 1995
  10. J Woodfill and B. Von Herzen, 'Real-time stereo vision on the PARTS recon-figurable computer,' Proc. IEEE Workshop FPGAs for Custom Computing Machines, pp. 242-250, 1997 https://doi.org/10.1109/FPGA.1997.624620
  11. A. Darabiha, W. J. Mac Lean, and J. Rose, 'Reconfigurable hardware implementation of a phase-correlation stereo algorithm,' Machine Vision and Applications, Vol.17, No.2, pp.l16-132, May 2006 https://doi.org/10.1007/s00138-006-0018-2
  12. C. Kuglin and D. Hines, 'The phase correlation image alignment method,' Proc. IEEE Int. Conf., Cybem, Soc., pp. 163-165, 1975
  13. W. T. Freeman and E. H. Adelson, 'The design and use of steerable filters,' PAMI, Trans. on, Vol.13, Issue 9, pp. 891-906, Sept. 1991 https://doi.org/10.1109/34.93808
  14. C. Cuadrado, A. Zuloaga, J. L. Martin, J. Laizaro, and J. Jimenez, 'Real-Time Stereo Vision Processing System in a FPGA IEEE Industrial Electronics,' IECON 2006 - 32nd Annual Conference, pp.3455-3460, Nov. 2006 https://doi.org/10.1109/IECON.2006.347755
  15. M. Gong and Y. H. Yang, 'Near real-time reliable stereo matching using programmable graphics hardware,' IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 2005. CVPR 2005. Vol.1, pp.924-931, 20-25 June 2005 https://doi.org/10.1109/CVPR.2005.246
  16. IEEE, IEEE standard VHDL Language Reference Manual, std 1076-1993, New York, 1993
  17. www.xilinx.com/ise/logic_design_prod/webpack.htm