전기학회논문지 (The Transactions of The Korean Institute of Electrical Engineers)

  • 제56권11호
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  • Pages.2017-2022
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  • 2007
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  • 1975-8359(pISSN)
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  • 2287-4364(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

면적 및 전력소모 감소를 위한 효율적인 ROM 설계

The Effective ROM Design for Area and Power Dissipation Reduction

  • 발행 : 2007.11.01
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초록

In a memory, most power is dissipated in line of high capacitance such as decoder lines, word lines, and bit * lines. The decoder size as well as the parastic capacitances of the bit-line are going to reduce, if ROM core size reduces. This paper proposes to reduce a mathod of power dissipation for reducing ROM core size. Design result of ROM used in FFT[2], proposed method lead to up to 40.6%, 42.12%, 37.82% reduction in area, power consumption and number of Tr. respectively compared with previous method.

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참고문헌

  1. M. Hiraki, 'Data-dependent logic swing internal bus architecture for ultra low-power LSls,' in Proc. IEEE J. Solid-State Circuits Conf., 1995, pp. 397-402
  2. E. Bertagnolli, F. Hofmann, J.Willer, R. Mary, F. Lau, P. W. von Basse, M. Bollu, R. Thewes, U. Kollmer, U. Zimmermann, M. Hain, W. H. Krautschneider, A. Rusch, B. Hasler, A. Kohlhase, and H. Klose, 'ROS: An extremely high mask ROM technology based on vertical transistorcells,' in VLSI Technology Dig. Tech Papers Symp., 1996, pp. 58-59
  3. R. Kanan, A. Guyot, B. Hochet, and M. Delclercq, 'A divided decodermatrix (DDM) structure and its application to a 8 Kb GaAs MESFET ROM,' In Proc. IEEE Int. Circuits Systems Symp., vol. 3, June 1997, pp. 1888-1891
  4. Y. Naruke, T. Iwase, M. Takizawa,K. Saito, M. Asano, H. Nishmura, and T. Mochizuki, 'A 16 Mb mask ROM with programmable redundancy,' in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1989, pp. 128-129
  5. B.-D. Yang and L.-S. Kim, 'A low power charge recycling ROM architecture,'IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 8, pp. 590-600, Aug. 2003 https://doi.org/10.1109/TVLSI.2003.816138