The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
권호 표지

Design of Digital Signal Processor for Ethernet Receiver Using TP Cable

TP 케이블을 이용하는 이더넷 수신기를 위한 디지털 신호 처리부 설계

  • Published : 2007.08.31
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.

본 논문에서는 TP 케이블을 이용하여 100Mbps의 전송 속도를 지원하는 100Base-TX Ethernet 수신기의 디지털 신호 처리부를 제안하였다. 제안하는 디지털 신호 처리부는 자동 이득 조절기, 심볼 동기 복원기, 적응 등화기, BLW 보정기로 구성되어 있으며 초기 위상에 상관없이 150m까지 $10^{-12}BER$이하의 성능을 보였다. 제안하는 신호 처리부는 일부 블록을 제외한 모든 부분을 디지털로 구현하였으며 적응 등화기와 BLW 보정기 연동 구조는 기존의 적응 등화기 에러 값을 이용하는 구조에 비하여 MSE가 약 1dB정도의 성능 향상을 가져왔다. 설계한 디지털 신호 처리부는 Verilog-HDL로 구현되었으며 삼성 $0.18{\mu}m$ 라이브러리를 사용하여 합성 결과 동작 속도는 7.01ns 이며 총 게이트 수는 128.528 게이트였다.

Keywords

References

  1. IEEE, Part3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications, IEEE Std. 802.3, 2002
  2. ANSI, Fiber distributed data interface (FDDI) - token ring twisted pair physical layer medium dependent (TP-PMD), ANSI x3.263-1995, Sep. 1995
  3. Intel corporation, LXT972A data sheet, Available : http://www.intel.com
  4. Broadcom corporation, BMC5208 data sheet, Available : http://www.broadcom. com
  5. Mysticom corporation, MystiPHY110 product brief, Available : http://www. mysticom.com
  6. Jae Hyung Baek, Ju hyung Hong, and Myung H. Sunwoo, 'Novel Digital Signal Processing Unit for Ethernet Receiver,' in proc. IEEE Int. Symp. Circuits Syst. (ISCAS'2005), May 2005, pp. 4477-4480
  7. Jim Rivernider, 'Return loss and data transmission,' Available : http://www.quabbin. com
  8. K. H. Mueller and M. Muller, 'Timing recovery in digital synchronous data recievers,' IEEE Trans. Commun., vol. COM-24, pp.516-531, May 1976
  9. S. Huss, M. Mullen, and C.T. Gray, 'A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 $\mu$m CMOS technology,' in proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 135-138
  10. J. H. Lee, W. H. Park, J. H. hong, M. H. Sunwoo and K. H. Kim, 'A high-speed blind DFE equalizer using an error feedback filter for QAM modems,' in proc. IEEE Int. Symp. Circuits Syst. (ISCAS' 2003), May 2003, pp.464-467
  11. Douglas L. Jones, 'Learning characteristics of transpose-form LMS adaptive filters,' IEEE Trans. Circuits Syst. II, vol 39, pp. 745-749, Oct. 1992 https://doi.org/10.1109/82.199901
  12. Mel Buzes, ' Method and apparatus for reducing baseline wander,' United States, Patent 6,140,857, Mar. 29, 1999
  13. Leon Chia-Liang Lin and Gerchih Chou, 'Automatic gain control for communication receivers,' United States, Patent US 2003/0142659 A1. Jun. 25, 2002
  14. I. Greiss and E. Lida, 'Digital base-band Receiver,' United States, Patent US 2002/0021767 A1, Jun. 7, 2001
  15. Sren A. Raghavan, ' Digital baseline wander correction sircuit,' United States, Patent US 6,415,003 B1, Sep. 11, 1998
  16. Jyh-Ting Lai, 'Receiver for baseline wandering compensation,' United States, Patent US 2003/0206604 A1, Jul. 12, 2002