전기학회논문지 (The Transactions of The Korean Institute of Electrical Engineers)

  • 제56권4호
  • /
  • Pages.745-750
  • /
  • 2007
  • /
  • 1975-8359(pISSN)
  • /
  • 2287-4364(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

최적 범위내에서 WLS인 게이트 수가 최대가 되는 입력 벡터를 이용한 게이트 수정 기법

A Gate Modification Method Using the Input Vector Maximizes the Number of Gates in WLS within the Optimum Range

  • 발행 : 2007.04.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

In this paper, we propose a new gate modification method using the input vector maximizes the number of gates in WLS within the optimum range of the minimum leakage power. We prove that MLV is not always the optimal solution, and that the leakage power and area can decrease when modifying the gates using the input vector for which the number of gates in WLS is maximized within the optimum range of the minimum leakage power for the circuits applying the IVC technique and gate modification method. Using the proposed method, the gate-level description circuit can be converted to the modified circuit which reduces the leakage power by chip designer, and the modified circuit can be applied without any modification in design flow.

키워드

참고문헌

  1. D. Blaauw, A. Devgan, and F. Najm, 'Leakage power: trends, analysis and avoidance,' ASP-DAC 2005, vol. 1, pp. T-2, Jan. 2005
  2. http://public.itrs.net
  3. http://www-device.eecs.berkeley.edu/-ptm
  4. J. Halter and F. Najrn, 'A gate-level leakage power reduction method for ultra low power CMOS circuits,' CICC 1997, pp. 475 - 478. May. 1997
  5. S. Yang et al., 'Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits,' VLSI Design 2005, pp. 165-170 , Jan. 2005
  6. L. Yuan and G. Qu, 'A combined gate replacement and input vector control approach for leakage current reduction,' IEEE Transactions on Very Large Scale Integration Systems, vol. 14, no. 2, pp. 173-182, Feb. 2006 https://doi.org/10.1109/TVLSI.2005.863747
  7. H. Rahman and C. Chakrabarti, 'An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits,' IEEE Transactions on Circuits and Systems II, vol. 52, no. 8, pp. 496-500, Aug. 2005 https://doi.org/10.1109/TCSII.2005.849026
  8. N. Hanchate and N. Ranganathan, 'LECTOR: a technique for leakage reduction in CMOS circuits,' IEEE Transactions on Very Large Scale Integration Systems, vol. 12, no. 2, pp. 196-205, Feb. 2004 https://doi.org/10.1109/TVLSI.2003.821547
  9. Y. Xu, Z. Luo,and Xiaowei Li, 'A maximum total leakage current estimation method,' ISCAS 2004, vol. 2, pp. 757-760, May. 2004
  10. Z. Chen, M. Johnson, L. Wei, and K. Roy, 'Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks,' ISLPED 1998, pp. 239 - 244, Aug. 1998
  11. M. C. Johnson, D. Somasekhar, and K. Roy, 'Models and algorithms for bounds on leakage in CMOS circuits:' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 6, pp. 714 - 725, Jun. 1999 https://doi.org/10.1109/43.766723
  12. R. M. Rao, F. Liu, J. L. Burns, and R. B. Brown, 'A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits:' ICCAD 2003, pp. 689 - 692, Nov. 2003
  13. S. Naidu and E. Jacobs, 'Minimizing Stand-By Leakage Power in Static CMOS Circuits,' DATE 2001, pp 370 - 376, March. 2001
  14. F. Aloul, S. Hassoun, K. Sakallah, and D. Blaauw, 'Robust SAT-based search algorithm for leakage power reduction,' International Workshop. on Integrated Circuit Design, pp. 167 - 177, Sep. 2002
  15. F. Gao and J. P. Hayes, 'Exact and heuristic approaches to input vector control for leakage power reduction,' ICCAD 2004, pp. 527 - 532, Nov. 2004
  16. A. Abdollahi, F. Fallah, and M. Pedram, 'Analysis and optimization of static power considering transition dependency of leakage current in VLSI circuits,' ISQED 2005, pp, 77-82, March. 2005
  17. M. Johnson, D. Sornasekhar, and K. Roy, 'Leakage control with efficient use of transistor stacks in single threshold CMOS,' DAC 1999, pp. 442 - 445, Jun. 1999