고성능 프로세서를 위한 분기 명령어의 동적 History 길이 조절 기법

Dynamic Per-Branch History Length Fitting for High-Performance Processor

  • 곽종욱 (삼성전자반도체, SOC 연구소) ;
  • 장성태 (수원대학교 컴퓨터학과) ;
  • 전주식 (서울대학교 전기컴퓨터공학부)
  • 발행 : 2007.03.25

초록

분기 명령어에 대한 분기 예측 정확도는 시스템 전체의 성능 향상에 중대한 영향을 미친다. 본 논문에서는 분기 예측의 정확도를 높이기 위한 방법의 하나로, 각 분기 명령어 별로 사용되는 History 길이를 동적으로 조절할 수 있는 "각 분기별 동적 History 길이 조절 기법"을 소개한다. 제안된 기법은, 분기 예측에 있어서 관련된 레지스터들 사이의 데이터 종속성을 추적하여, 최종적으로 관련이 있는 레지스터를 포함하도록 유도하는 분기를 파악한 후, 관련 분기의 History만을 사용하게 해 주는 방식이다. 이를 위해 본 논문에서는, 데이터 종속성을 추적할 수 있는 알고리즘과 관련 하드웨어 모듈을 소개하였다. 실험 결과 제안된 기법은, 기존의 고정 길이 History를 사용하는 방식에 비하여 최대 5.96% 분기 예측 정확도의 향상을 가져 왔으며, 프로파일링을 통해 확인된 각 응용 프로그램 별 Optimal History 길이와 비교해서도 성능 향상을 보였다.

Branch prediction accuracy is critical for the overall system performance. Branch miss-prediction penalty is the one of the significant performance limiters for improving processor performance, as the pipeline deepens and the instruction issued per cycle increases. In this paper, we propose "Dynamic Per-Branch History Length Fitting Method" by tracking the data dependencies among the register writing instructions. The proposed solution first identifies the key branches, and then it selectively uses the histories of the key branches. To support this mechanism, we provide a history length adjustment algorithm and a required hardware module. As the result of simulation, the proposed mechanism outperforms the previous fixed static method, up to 5.96% in prediction accuracy. Furthermore, our method introduces the performance improvement, compared to the profiled results which are generally considered as the optimal ones.

키워드

참고문헌

  1. E. Sprangle and D. Carmean. 'Increasing processor performance by implementing deeper pipelines'. In Proc. 29th Int'l Symp. on Computer Architecture, pp. 25-34, 2002
  2. T.-Y. Yeh and Y. N. Patt, 'Alternative implementations of two-level adaptive branch prediction,' In Proc. of the 19th ISCA, pp. 124-134, May, 1992
  3. J. W. Kwak, J.-H. Kim, and C. S. Jhon, 'The Impact of Branch Direction History combined with Global Branch History in Branch Prediction', IEICE Transactions on Information and System, Vol. E88-D, No. 7, pp. 1754-1758, July 2005 https://doi.org/10.1093/ietisy/e88-d.7.1754
  4. K. Skadron, M. Martonosi, and D. Clark. 'Speculative updates of local and global branch history: A quantitative analysis', JILP, vol. 2, Jan. 2000
  5. P. Michaud, A. Seznec and R. Uhlig, 'Trading conflict and capacity aliasing in conditional branch predictors', 24th Intl. Symp. on Computer Architecture, pp. 292-303, 1997
  6. A. Seznec and P. Michaud. De-aliased Hybrid Branch Predictors. Technical Report No. 3618, Institut National de Recherche en Informatique etn Automatique (INRIA), February 1999
  7. M. Evers, S. J. Patel, R. S. Chapell, and Y. N. Patt, 'An analysis of correlation and predictability: What makes two-level branch predictors work', In Proceedings of the 25th Annual Intl. Symposium on Computer Architecture, pages 52-61, June 1998
  8. T. Juan, S. Sanjeevan, and J. J. Navarro, 'Dynamic history length fitting: A third level of adaptivity for branch prediction', In Proc. 25th Int'l Symp. on Computer Architecture, pages 155-166, 1998
  9. M.-D. Tarlescu, K. B. Theobald, and G. R. Gao, 'Elastic history buffer: A low-cost method to improve branch prediction accuracy', In Proc. Int'l Conf. on Computer Design, pages 82-87, 1997
  10. J. Stark, M. Evers, and Y. N. Patt, 'Variable length path branch prediction', In Proc. 8th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pages 170-179, 1998
  11. A. Seznec, S. Felix, V. Krishnan, and Y. Sazeid'es. 'Design tradeoffs for the ev8 branch predictor', In Proc. of the 29th ISCA, pp. 295-306, May 2002
  12. A. R. Talcott,W. Yamamoto,M. J. Serrano, R. C.Wood, and M. Nemirovsky, 'The impact of unresolved branches on branch prediction scheme performance,' in Proceedings of the 21st Annual International Symposium on Computer Architecture, pp. 12-21, Apr. 1994
  13. E. Hao, P.-Y. Chang, and Y. Patt, 'The effect of speculatively updating branch history on branch prediction accuracy, revisited,' in Proceedings of the 27th Annual International Symposium on Microarchitecture, pp. 228-232, Nov. 1994
  14. McFarling, S., 'Combining branch predictors. Tech. Rep. TN-36m', Digital Western Research Lab., June, 1993
  15. A. R. Talcott, M. Nemirovsky, and R. C. Wood, 'The Influence of Branch Prediction Table Interference on Branch Prediction Scheme Performance', International Conference on Parallel Architectures and Compilation Techniques, 1995
  16. D. Burger, T. M. Austin, and S. Bennett, 'Evaluating future micro-processors: the SimpleScalar tool set', Tech. Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept., 1997
  17. SPEC CPU2000 Benchmarks, http://www.specbench.org
  18. D. A. Jimenez, S. W. Keckler, and C. Lin, 'The impact of delay on the design of branch predictors', In Proc. 33rd Int'l Symp. on Microarchitecture, pp. 67-76, 2000