• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.2 s.314
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• pp.1-10
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• 2007

Branch prediction accuracy is critical for the overall system performance. Branch miss-prediction penalty is the one of the significant performance limiters for improving processor performance, as the pipeline deepens and the instruction issued per cycle increases. In this paper, we propose "Dynamic Per-Branch History Length Fitting Method" by tracking the data dependencies among the register writing instructions. The proposed solution first identifies the key branches, and then it selectively uses the histories of the key branches. To support this mechanism, we provide a history length adjustment algorithm and a required hardware module. As the result of simulation, the proposed mechanism outperforms the previous fixed static method, up to 5.96% in prediction accuracy. Furthermore, our method introduces the performance improvement, compared to the profiled results which are generally considered as the optimal ones.