References
- E. Sprangle and D. Carmean. 'Increasing processor performance by implementing deeper pipelines'. In Proc. 29th Int'l Symp. on Computer Architecture, pp. 25-34, 2002
- T.-Y. Yeh and Y. N. Patt, 'Alternative implementations of two-level adaptive branch prediction,' In Proc. of the 19th ISCA, pp. 124-134, May, 1992
- J. W. Kwak, J.-H. Kim, and C. S. Jhon, 'The Impact of Branch Direction History combined with Global Branch History in Branch Prediction', IEICE Transactions on Information and System, Vol. E88-D, No. 7, pp. 1754-1758, July 2005 https://doi.org/10.1093/ietisy/e88-d.7.1754
- K. Skadron, M. Martonosi, and D. Clark. 'Speculative updates of local and global branch history: A quantitative analysis', JILP, vol. 2, Jan. 2000
- P. Michaud, A. Seznec and R. Uhlig, 'Trading conflict and capacity aliasing in conditional branch predictors', 24th Intl. Symp. on Computer Architecture, pp. 292-303, 1997
- A. Seznec and P. Michaud. De-aliased Hybrid Branch Predictors. Technical Report No. 3618, Institut National de Recherche en Informatique etn Automatique (INRIA), February 1999
- M. Evers, S. J. Patel, R. S. Chapell, and Y. N. Patt, 'An analysis of correlation and predictability: What makes two-level branch predictors work', In Proceedings of the 25th Annual Intl. Symposium on Computer Architecture, pages 52-61, June 1998
- T. Juan, S. Sanjeevan, and J. J. Navarro, 'Dynamic history length fitting: A third level of adaptivity for branch prediction', In Proc. 25th Int'l Symp. on Computer Architecture, pages 155-166, 1998
- M.-D. Tarlescu, K. B. Theobald, and G. R. Gao, 'Elastic history buffer: A low-cost method to improve branch prediction accuracy', In Proc. Int'l Conf. on Computer Design, pages 82-87, 1997
- J. Stark, M. Evers, and Y. N. Patt, 'Variable length path branch prediction', In Proc. 8th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pages 170-179, 1998
- A. Seznec, S. Felix, V. Krishnan, and Y. Sazeid'es. 'Design tradeoffs for the ev8 branch predictor', In Proc. of the 29th ISCA, pp. 295-306, May 2002
- A. R. Talcott,W. Yamamoto,M. J. Serrano, R. C.Wood, and M. Nemirovsky, 'The impact of unresolved branches on branch prediction scheme performance,' in Proceedings of the 21st Annual International Symposium on Computer Architecture, pp. 12-21, Apr. 1994
- E. Hao, P.-Y. Chang, and Y. Patt, 'The effect of speculatively updating branch history on branch prediction accuracy, revisited,' in Proceedings of the 27th Annual International Symposium on Microarchitecture, pp. 228-232, Nov. 1994
- McFarling, S., 'Combining branch predictors. Tech. Rep. TN-36m', Digital Western Research Lab., June, 1993
- A. R. Talcott, M. Nemirovsky, and R. C. Wood, 'The Influence of Branch Prediction Table Interference on Branch Prediction Scheme Performance', International Conference on Parallel Architectures and Compilation Techniques, 1995
- D. Burger, T. M. Austin, and S. Bennett, 'Evaluating future micro-processors: the SimpleScalar tool set', Tech. Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept., 1997
- SPEC CPU2000 Benchmarks, http://www.specbench.org
- D. A. Jimenez, S. W. Keckler, and C. Lin, 'The impact of delay on the design of branch predictors', In Proc. 33rd Int'l Symp. on Microarchitecture, pp. 67-76, 2000