참고문헌
- 'International Technology Roadmap for Semiconductors,' SIA Report, 2006
- A. Deutsch et al., 'On-chip wiring design challenges for gigahertz operation,' Proc. IEEE, vol. 89, no. 4, pp. 529-555, Apr. 2001 https://doi.org/10.1109/5.920582
- Y. Massoud and Y. Ismail, 'Grasping the impact of on-chip inductance,' IEEE Circuits and Devices, vol. 17, no. 4, pp. 14-21, Jul. 2001
- T. Sakurai, 'Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's,' IEEE Trans. Electron Devices, vol. 40, no.1, pp.118-124, Jan. 1993 https://doi.org/10.1109/16.249433
- J. Zhang and E. G. Friedman, 'Effect of shield insertion on reducing crosstalk noise between coupled interconnects,' in IEEE Int. Symp. on Circuit and Systems, pp. 529-532,2004
- K. Agarwal, D. Sylvester, and D. Blaauw, 'Modeling and analysis of crosstalk noise in coupled RLC interconnects,'IEEE Trans. Computer-Aided Design, vol. 25, no. 5, pp. 892-901, May 2006 https://doi.org/10.1109/TCAD.2005.855961
- J. E. Lorival et al., 'Analytical expressions for capacitive and inductivecoupling,' in IEEE Workshop on SPI, pp. 115-118, 2006
- L.Yin and L. He, 'An efficient analytical model of coupled on-chip RLC interconnects,' in Proc. ASPDAC, pp. 385-390, 2001
- J. E. Lorival, D. Deschacht, Y. Quere, T. L. Gouguec, and F. Huret, 'Additivity of capacitive and inductive coupling in submicronic interconnects,' in IEEE DTIS, pp. 300-304,2006
- Y. Eo, J. Shim, and W. R. Eisenstadt, 'A travelingwave- based waveform approximation technique for the timing verification of single transmission lines,' IEEE Trans. Computer-Aided Design, vol. 21, no. 6, pp. 723-730, June 2002 https://doi.org/10.1109/TCAD.2002.1004316
- C. R. Paul, Analysis of Multiconductor Transmission Lines. New York: Wiley, 1994
-
P. Bai et al., 'A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57
$\mu$ m2 SRAM cell' in IEEE Int. Electron Device Meeting, pp.657-660,2004 - Y. I. Ismail, Eby. G. Friedman, and Jose L. Neves, 'Figures of merit to characterize the importance of on-chip inductance,' IEEE Trans. VLSI., vol. 7, no. 4, pp. 442-449, Dec. 1999 https://doi.org/10.1109/92.805751
피인용 문헌
- A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control vol.44, pp.11, 2009, https://doi.org/10.1109/JSSC.2009.2028917
- Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces vol.33, pp.2, 2010, https://doi.org/10.1109/TADVP.2009.2033938
- A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS vol.59, pp.1, 2012, https://doi.org/10.1109/TCSI.2011.2161394