DOI QR코드

DOI QR Code

A Fully Integrated 5-GHz CMOS Power Amplifier for IEEE 802.11a WLAN Applications

  • Baek, Sang-Hyun (Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology) ;
  • Park, Chang-Kun (Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology) ;
  • Hong, Song-Cheol (Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology)
  • 발행 : 2007.06.30

초록

A fully integrated 5-GHz CMOS power amplifier for IEEE 802.11a WLAN applications is implemented using $0.18-{\mu}m$ CMOS technology. An on-chip transmission-line transformer is used for output matching network and voltage combining. Input balun, inter-stage matching components, output transmission line transformer and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier occupies a total area of $1.7mm{\times}1.2mm$. At a 3.3-V supply voltage, the amplifier exhibits a 22.6-dBm output 1-dB compression point, 23.8-dBm saturated output power, 25-dB power gain. The measured power added efficiency (PAE) is 20.1 % at max. peak, 18.8% at P1dB. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12dBm of average power at the EVM of -25dB.

키워드

참고문헌

  1. Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High Speed Physical Layer in the 5 GHz Band, IEEE Std. 802.11a-1999, Sep. 1999
  2. Tirdad Sowlati and Domine M. W. Leenaerts, 'A 2.4-GHz 0.18-${\mu}m$ CMOS self-biased cascode power amplifier,' IEEE J. Solid-State Circuits, vol. 38, pp. 1318-1324, Aug. 2003 https://doi.org/10.1109/JSSC.2003.814417

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