References
- Pinhong Chen, Kurt Keutzer, 'Toward True Crosstalk Noise Analysis' on Dept. of EECS, Univ. of California at Berkeley, in 1999 IEEE
- Yasuhiko Sasaki, Giovanni De Micheli, 'Crosstalk Delay Analysis using Relative Window Method' on stanford University Computer System Laboratory, in 1999 IEEE
- Tong Xiao, Malgorzata Marek-Sadowska 'Worst Delay Estimation in Crosstalk Aware Static Timing Analysis' on Department of Electrical and Computer Engineering University of California, in 2000 IEEE
- Pinhong Chen, Yuji Kukimoto, Kurt Keutzer, 'Refining Switching Window by Time Slots for Crosstalk Noise Calculation', on Dept. of EECS, U.C. Berkeley, Cadence Design System Inc, in 2002 IEEE
- Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong, 'Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis' on CAE team, Memory Division, Dept. of Device solution Network, Samsung Electronics, in 2003 IEEE
- Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska, 'Temporo functional Crosstalk Noise Analysis', on Cadence Design System, in DAC 2003, June 2-6, Anaheim, California, USA
- M. Hashimoto, H. Onodera, and K. Tamaru, 'A Power Optimization Method Considering Glitch Reduction by Gate Sizing', in Proceedings of the Inter national Symposium on Low Power Design, pp. 221-226, August 1998
- J. Kim, C. Bamji, Y. Jiang, and S. Sapatnekar, , 'Concurrent Transistor Sizing and Buffer Insertion by Considering Cost-Delay Tradeoffs',, in Proceedings of the International Symposium on Physical Design, pp. 130-135, April 1997
- A.Rubio, N.Itazaki, X.Zu, and K.Kinoshita. 'An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits'. IEEE Trans. on Computer-Aided Design, 13:387-394, Mar. 1994 https://doi.org/10.1109/43.265680
- Sachin S. Sapatnekar and Weitong Chuang, , 'Power vs Delay in Gate Sizing: Conflicting Objectives?', in Proceedings of the 1995 IEEE/ACM International Conference of Computer-Aided Design, pp.463-466, 1995
- E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A .L. Sangiovanni- Vincentelli. 'SIS: A system for sequential circuit synthesis, Technical Report', UCB/ERL M92/41, Electronics Research Lab, University of California at Berkeley, 1992