Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

IEEE 1500 Wrapper and Test Control for Low-Cost SoC Test

저비용 SoC 테스트를 위한 IEEE 1500 래퍼 및 테스트 제어

  • Yi, Hyun-Bean (Dept. of Computer Science & Engineering, Hanyang University) ;
  • Kim, Jin-Kyu (Dept. of Computer Science & Engineering, Hanyang University) ;
  • Jung, Tae-Jin (Dept. of Computer Science & Engineering, Hanyang University) ;
  • Park, Sung-Ju (Dept. of Electronical Engineering Computer Science, Hanyang Univ.)
  • 이현빈 (한양대학교 컴퓨터공학과) ;
  • 김진규 (한양대학교 컴퓨터공학과) ;
  • 정태진 (한양대학교 컴퓨터공학과) ;
  • 박성주 (한양대학교 전자 컴퓨터 공학과)
  • Published : 2007.11.25
Download PDF
⟨ Previous Next ⟩

Abstract

This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.

본 논문에서는 저비용 SoC 테스트를 위한 테스트 설계 기술에 대해서 다룬다. IEEE 1500 랩드 코어를 SoC TAP (Test Access Port) 을 통하여 스캔 테스트를 수행하는 방법을 제시하고, 지연고장 테스트를 위한 테스트 클럭 생성회로를 설계한다. TAP의 신호만을 이용하여 SoC 테스트를 수행함으로써 테스트 핀 수를 줄일 수 있고, SoC 내부의 회로를 사용하여 지연고장 테스트를 수행함으로써 저가의 테스트 장비를 사용할 수 있다. 실험을 통하여 제시한 방식의 효율성을 평가하고, 서로 다른 주파수의 클럭을 사용하는 여러 코어의 지연고장 테스트를 동시에 수행 할 수 있음을 확인한다.

Keywords

References

  1. R. A. Parekhji, 'DFT for Low Cost SOC Test,' Proceedings of IEEE Asian Test Symposium, pp. 451, Dec. 2005
  2. H. Hashempour, F. J. Meyer, and F. Lombardi, 'Analysis and Evaluation of Multisite Testing for VLSI,' IEEE Transactions on Instrumentation and Measurement, Vol. 54, pp. 1770-1778, Oct. 2005 https://doi.org/10.1109/TIM.2005.855099
  3. H. Vranken, T. Waayers, H. Fleury, and D. Lelouvier, 'Enhanced Reduced Pin-Count Test for Full-Scan Design,' Proceedings of IEEE International Test Conference, pp. 738-747, 2001
  4. J. Jahangiri, N. Mukherjee, C. Wu-Tung, S. Mahadevan, and R. Press, 'Achieving High Test Quality with Reduced Pin Count Testing,' Proceedings of IEEE Asian Test Symposium, pp. 312-317, Dec. 2005
  5. M. Beck, O. Barondeau, M. Kaibel, F. Poehl, L.ub Xijiang and R. Press, 'Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality,' Proceedings of the Design, Automation and Test in Europe, 2005
  6. IEEE Computer Society, 'IEEE Standard Testability Method for Embedded Core-based Integrated Circuits,' Aug. 2005
  7. J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, 'Embedded Deterministic Test,' IEEE Transactions on CAD, Vol. 23, pp. 776-792, May 2004 https://doi.org/10.1109/TCAD.2004.826558
  8. B. I. Dervisoglu, 'A Unified DFT Architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers,' Proceedings of Design Automation Conference, pp. 53-58, June 2001
  9. L. Whetsel, 'Inevitable Use of TAP Domains in SoCs,' Proceedings of IEEE International Test Conference, pp. 1191, 2002
  10. Y. Zorian, A. Yessayan, 'IEEE 1500 utilization in SOC design and test,' Proceedings of IEEE International Test Conference, Nov. 2005
  11. M. Schrader, R. McConnell, 'SoC Design and Test Considerations,' Design Automation and Test in Europe Conference and Exhibition, pp. 202-207, 2003
  12. E. J. Marinissen, S. K. Goel, and M. Lousberg, 'Wrapper design for embedded core test,' Proceedings of IEEE International Test Conference, pp. 911 - 920, Oct. 2000
  13. J. Savir and S. Patil, 'Scan-Based Transition Test,' IEEE Transactions on Computer-Aided Design of Integrated Circuit and System, Vol. 12, Aug. 1993
  14. J. Savir and S. Patil, 'Broad-Side Delay Test,' IEEE Transactions on Computer-Aided Design of Integrated Circuit and System, Vol. 13, Aug. 1994
  15. J. Saxena, K. M. Butler, J. Gatt, R. Raghuraman, S. P. Kumar, S. Basu, D. J. Campbell, J. Berech, 'Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges,' Proceedings of IEEE International Test Conference, pp 1120-1129, 2002
  16. S. Wang, X. Liu, S. T. Chakradhar, 'Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets,' Proceedings of Design Automation and Test in Europe, pp. 1296-1301, 2004
  17. Synopsys On-Line Documentation, Vol. 1, 2003
  18. E. J. Marinissen, V. Iyengar, and K. Chakrabarty, ITC'02 SOC Test Benchmarks. Available: http://www.hitech-projects.com/itc02socbenchm/