Abstract
As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.
