Journal of the Institute of Electronics Engineers of Korea TC (대한전자공학회논문지TC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A New Design-for-Testability Circuit for Low Noise Amplifiers

저잡음 증폭기를 위한 새로운 구조의 검사용 설계회로

  • Ryu Jee-Youl (Department of Electrical Engineering, Arizona State University) ;
  • Noh Seok-Ho (Major of Electronic Engineering, College of Electronic & Information Engineering, Andong National University)
  • 류지열 (애리조나주립대학 전기공학과) ;
  • 노석호 (안동대학교 전자공학과)
  • Published : 2006.03.01
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Abstract

This paper presents a new Design-for-Testability (DfT) circuit for 4.5-5.5GHz low noise amplifiers (LNAs). The DfT circuit measures gain, noise figure, input impedance, input return loss, and output signal-to-noise ratio for the LNA without external expensive equipment. The DfT circuit is designed using 0.18m SiGe technology. The circuit utilizes input impedance matching and DC output voltage measurements. The technique is simple and inexpensive.

본 논문에서는 4.5-5.5GHz 저잡음 증폭기 (low noise amplifiers, LNAs)를 위한 새로운 구조의 검사용 설계(Design-for-Testability, DfT) 회로를 제안한다. 이러한 검사용 설계회로는 고가의 장비를 사용하지 알고도 저잡음 증폭기의 전압 이득, 잡음 지수, 입력 임피던스, 입력 반사 손실 및 출력 신호대 잡음 전력비를 측정한다. 검사용 설계회로는 $0.18{\mu}m$ SiGe 공정을 이용하여 설계되었으며, 입력 임피던스 정합과 직류 출력 전압 측정을 이용한다. 이러한 회로를 이용한 회로 검사 기술은 검사 방법이 간단하고 검사하는데 드는 비용이 저렴하다.

Keywords

References

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