대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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디지털 회로에서의 새로운 모델 기반 IP-Level 소모 전력 추정 기법

New Model-based IP-Level Power Estimation Techniques for Digital Circuits

  • 이창희 (한양대학교 전자컴퓨터공학부) ;
  • 신현철 (한양대학교 전자컴퓨터공학부) ;
  • 김경호 (삼성전자 정보통신총괄 통신연구소)
  • Lee, Chang-Hee (School of Electrical and Computer Engineering Hanyang University) ;
  • Shin, Hyun-Chul (School of Electrical and Computer Engineering Hanyang University) ;
  • Kim, Kyung-Ho (Telecom R&D Center, Telecommunication Networks Samsung Electronics)
  • 발행 : 2006.02.01
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초록

반도체 공정기술의 발달로 인해 칩의 집적도가 향상되고 높은 성능의 SoC (System On a Chip)의 구현이 가능해졌다. 하지만 이로 인한 칩의 전력 소모량 증가는 칩 설계시의 중요 제한 요소가 되고 있다 칩 설계의 하위 단계로 갈수록 설계의 수정은 시간과 금전적 비용을 기하급수적으로 증가시키기 때문에, 설계의 상위 단계에서부터 칩의 소모 전력을 미리 추정하는 기술은 필수적이다. 이에 본 연구에서는 효율적인 상위 레벨 소모 전력 추정을 위해 회로를 레벨화 하고, 일부 레벨의 스위칭을 기반으로 회로의 소모 전력을 look up 테이블을 이용하여 모델링하였다 제안한 기술을 이용하여 ISCAS'85 벤치마크 회로에 대해 평균 소모 전력을 추정한 결과, 기존에 알려진 소모 전력 추정 기술에 비해 평균 추정 오차를 $9.45\%$에서 $3.84\%$로 크게 개선한 결과를 얻을 수 있었다.

Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.

키워드

참고문헌

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