전자공학회논문지CI (Journal of the Institute of Electronics Engineers of Korea CI)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

고속 다이나믹 십진 가산기 설계

High-Speed Dynamic Decimal Adder Design

  • 유영갑 (충북대학교 정보통신공학과) ;
  • 김용대 (충북대학교 정보통신공학과) ;
  • 최종화 (충북대학교 정보통신공학과)
  • You, Young-Gap (Department of Information & Communication Engineering, Chungbuk Nat'l University) ;
  • Kim, Yong-Dae (Department of Information & Communication Engineering, Chungbuk Nat'l University) ;
  • Choi, Jong-Hwa (Department of Information & Communication Engineering, Chungbuk Nat'l University)
  • 발행 : 2006.11.25
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 십진수 가산에서 속도 개선을 위한 가산 회로를 제안하였다. 속도 개선을 위한 방법으로 빠른 캐리 전달 방식으로 알려진 캐리 예견(carry loohahead) 회로를 사용하였다. 또한 빠른 십진 연산을 위해 입력식의 간략화 및 다이나믹 구조를 적용함으로서 가산 출력 지연시간을 줄였다. 제안된 회로의 가산기 구현에서 $0.18{\mu}m$ CMOS 공정을 이용한 타이밍 시뮬레이션측정 결과, 16 디지트 가산에 걸리는 최대 지연시간은 0.83 ns로 나타났다. 제안된 방법은 다른 십진 가산 방식과 비교했을 때 가산에 따른 지연시간이 작다.

This paper proposed a carry lookahead (CLA) circuitry design. It was based on dynamic circuit aiming at delay reduction in an addition of BCD coded decimal numbers. The performance of these decimal adders is analyzed demonstrating their speed improvement. Timing simulation on the proposed decimal addition circuit employing $0.18{\mu}m$ CMOS technology yielded the worst-case delay of 0.83 ns at 16-digit. The proposed scheme showed a speed improvement compared to several schemes for decimal addition.

키워드

참고문헌

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