Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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VLSI design of a FNNPDS encoder for vector quantization

벡터양자화를 위한 FNNPDS 인코더의 VLSI 설계

  • Kim Hyeung-Cheol (Dept. of Electrical & Electronic Eng., Dongshin University) ;
  • Shim Jeong-Bo (Dept. of Electrical & Electronic Eng., Dongshin University) ;
  • Jo Je-Hwang (Dept. of Information & Communication Eng., Dongshin University)
  • 김형철 (동신대학교 전기전자공학과) ;
  • 심정보 (동신대학교 전기전자공학과) ;
  • 조제황 (동신대학교 정보통신공학부)
  • Published : 2005.02.01
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Abstract

We propose the design method for the VLSI architecture of FNNPDS combined PDS(partial distance search) and FNNS(fast nearest neighbor search), which are used to fast encoding in vector quantization, and obtain the results that FNNPDS(fast nearest neighbor partial distance search) is faster method than the conventional methods by simulation. In simulations, we investigate timing diagrams described searching time of the nearest codevector for an input vector, and compare the average clock cycles per input vector for Lena and Peppers images. According to the result of simulations, the number of the clock cycle of FNNPDS was reduced to $79.2\%\~11.7\%$ as compared with the number using the conventional techniques.

벡터양자화에서 고속 인코딩에 사용되는 기존 방법인 PDS(partial distance search)와 FNNS(fast nearest neighbor search)를 결합한 FNNPDS(fast nearest neighbor partial distance search)를 VISI로 구현하기 위한 설계 방법을 제안하고, 모의실험을 통해 FNNPDS가 다른 방법에 비해 보다 고속화가 이루어짐을 입증한다. 모의실험 방법은 임의의 입력벡터에 대해 최단거리 부호벡터를 찾는 타이밍도를 고찰하고, Lena와 Peppers 영상에 대한 입력벡터당 평균 클럭 사이클을 비교한다. 모의실험 결과에 의하면 FNNPDS의 클럭 사이클 수는 다른 방법들보다 $79.2\%\~11.7\%$ 감소되었다.

Keywords

References

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