ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Design and Architecture of Low-Latency High-Speed Turbo Decoders

  • Jung, Ji-Won (Department of Radio and Information Communication Engineering, Korea Maritime University) ;
  • Lee, In-Ki (Department of Radio and Information Communication Engineering, Korea Maritime University) ;
  • Choi, Duk-Gun (Department of Radio and Information Communication Engineering, Korea Maritime University) ;
  • Jeong, Jin-Hee (Department of Radio and Information Communication Engineering, Korea Maritime University) ;
  • Kim, Ki-Man (Department of Radio and Information Communication Engineering, Korea Maritime University) ;
  • Choi, Eun-A (Digital Broadcasting Division, ETRI) ;
  • Oh, Deock-Gil (Digital Broadcasting Division, ETRI)
  • Received : 2005.01.31
  • Published : 2005.10.31
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Abstract

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

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References

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