Transactions on Electrical and Electronic Materials

  • 제6권5호
  • /
  • Pages.225-228
  • /
  • 2005
  • /
  • 1229-7607(pISSN)
  • /
  • 2092-7592(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
권호 표지
DOI QR코드

DOI QR Code

A Study on the Optimized Copper Electrochemical Plating in Dual Damascene Process

  • Yoo, Hae-Young (School of Electrical and Electronics Engineering, Chung-Ang University) ;
  • Chang, Eui-Goo (School of Electrical and Electronics Engineering, Chung-Ang University) ;
  • Kim, Nam-Hoon (Research Institute of Energy Resources Technology, Chosun University)
  • 발행 : 2005.10.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

키워드

참고문헌

  1. W. C. Gau, T. C. Chang, Y. S. Lin, J. C. Hu, L. J. Chen, C. Y. Chang, and C. L. Cheng, 'Copper electroplating for future ultralarge scale integration interconnection', J. Vac. Sci. Technol. A, Vol. 18, Iss. 2, p. 656, 2000
  2. C. H. Ting, D. Papapanayiotou, and M. Zhu, 'Electro-chemical deposition technology for ULSI multilevel copper interconnects', 1998 5th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Beijing, China, p. 198, 1998
  3. M. Tsujimura, K. Mishima, J. Kunisawa, N. Makino, T. Matsuda, H. Kaneko, and K. Okumura, 'A novel compact ECD tool for ULSI Cu metallization', Proceedings of the ISSM 2000: The Ninth International Symposium on Semiconductor Manufacturing, Tokyo, Japan, p. 106, 2000
  4. H. Tenmei, T. Yamazaki, and Y. Narizuka, 'Study on planarizing process for high aspect ratio via-holes using for electroplating and apply to process for Cu/polyimide multilayer substrates', 2nd 1998 IEMT/IMC Symposium Proceeding, Tokyo Japan, p. 224, 1998
  5. J. Chen, S. Parikh, T. Vo, S. Rengarajan, T. Mandrekar, P. Ding, L. Chen, and R. Mosely, 'Barrier crystallographic texture control and its impact on copper interconnect reliability', Proceedings of the IEEE 2002 International Interconnect Technology Conference, San Francisco, CA, p. 185, 2002
  6. N. H. Kim, J. H. Lim, S. Y. Kim, and E. G. Chang, 'Effects of phosphoric acid stabilizer on copper and tantalum nitride CMP', Materials Letters, Vol. 57, No. 29, p. 4601, 2003
  7. N. H. Kim, J. H. Lim, S. Y. Kim, and E. G. Chang, 'Semi-abrasive free slurry with acid colloidal silica for copper chemical mechanical planarization', Journal of Materials Science: Materials in Electronics, Vol. 16, Iss. 9, p. 629, 2005
  8. S. Y. Kim, N. H. Kim, I. P. Kim, E. G. Chang, Y. J. Seo, and H. S. Chung, 'A study on the corrosion effects by addition of complexing agent in the copper CMP process', Trans. EEM, Vol. 4, No.6, p. 28, 2003

피인용 문헌

  1. Yield improvement of 0.13 μm Cu/low-k dual-damascene interconnection by organic cleaning process vol.25, pp.6, 2007, https://doi.org/10.1116/1.2794049