대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Tracking analog-to-digital 변환기를 이용한 digital phase-locked loop

Digitally controlled phase-locked loop with tracking analog-to-digital converter

  • 차수호 (한양대학교 전자통신컴퓨터공학부) ;
  • 유창식 (한양대학교 전자통신컴퓨터공학부)
  • Cha, Soo-Ho (Department of Electronics and Computer Engineering, Hanyang University) ;
  • Yoo, Chang-Sik (Department of Electronics and Computer Engineering, Hanyang University)
  • 발행 : 2005.09.01
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 1.6Gb/s에서 동작하는 digitally controlled phase-locked loop (DCPLL)를 제안한다. DCPLL은 일반적인 아날로그 PLL과 tracking analog-to-digital 변환기를 결합한 구조이다. 제안한 DCPLL에서는 tracking ADC의 출력이 voltage controlled oscillator (VCO)의 제어 전압을 생성한다. 일반적으로 사용되는 digital PLL (DPLL)은 digitally controlled oscillator (DCO)와 time-to-digit converter (TDC)로 구성된다 DCO와 TDC를 사용한 DPLL은 시간 스텝이 작을 수 록 jitter 특성이 향상되지만 전력소모는 커진다. 이 논문에서 제안한 DCPLL은 DPLL의 핵심요소인 DCO와 TDC를 사용하지 않았기 때문에 jitter, 면적, 전력소모 측면에서 유리하다. DCPLL은 $0.18\mu$m 4-metal CMOS공정을 이용하여 제작하였고 면적은 1mm $\times$0.35mm를 차지한다. 1.8V 단일 전원전압으로 정상동작에서는 59mW, power-down 모드에서는 $984\mu$W 전력을 소모하고 16.8ps rms jitter를 갖는다.

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

키워드

참고문헌

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