Mobility Reduction Scheduling for High-Level Synthesis

상위수준합성을 위한 배정가능범위 축소 스케줄링

  • 유희진 (순천제일대학 컴퓨터과학과) ;
  • 유희용 (동국대학교 컴퓨터공학과)
  • Published : 2005.08.01

Abstract

This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. The proposed approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that control step due to a violation against resource constraints, and so we can eliminate that control step among candidate assignable control steps. The proposed algorithm builds up a schedule based on gradual mobility reduction and finds a solution that yields high performance by evaluating on the impact on register assignment. Experiments on benchmarks show that this approach gains a considerable improvement over previous approaches.

본 논문은 자원제약 조건하에서 파이프라인 데이타패스 합성을 위한 스케줄링 방법을 제안한다. 제안 방법은 연산의 배정 가능한 제어단계들 중에서 처음과 마지막 제어단계에 임시로 연산을 배정하여 스케줄링 해가 존재하는지를 평가한다. 만약 해를 발견할 수 없다면 이는 자원제약 위반에 의해 연산을 그 제어단계에 배정하는 것이 불가능함을 의미하기 때문에 그 제어단계를 배정 가능한 제어단계 후보에서 제거한다 제안 알고리즘은 점진적 배정가능범위 축소에 기초하여 스케줄하고 자원 배정에 대한 영향을 고려하여 성능개선을 위한 해를 찾는다. 벤치마크에 대한 실험결과는 기존 방법들과 비교하여 개선된 실험결과를 보였다.

Keywords

References

  1. Narasimhan, M. and Ramanujam, J., 'Improving the computational performance of ILP-based problems,' Proc, of Int. Conf. on Computer-Aided Design, pp.593-596, 1998
  2. C. T. Hwang, Y. C. Hsu and Y. L. Lin 'Optimum and Heuristic Data Path Scheduling under Resource Constraints,' Proc. of the 27th Design Automation Conference, pp. 65-70 July 1990 https://doi.org/10.1109/DAC.1990.114831
  3. N. Park and A. C. Parker, 'Schwa: A software package for synthesis of pipelines from behavioral specification,' IEEE Trans. on Computer-Aided Design, vol. 7, pp. 356-370, March 1988 https://doi.org/10.1109/43.3169
  4. Hwang. C.T., Hsu. Y.C. and Lin. Y.L.. 'Scheduling for functional Pipelining and Loop Winding.' Proc. of the 28th Design Automation Conference. pp. 764-769. 1991
  5. Hwang, C.T., Hsu, Y.C. and Lin, Y.L., 'PLS: A scheduler for pipeline synthesis,' IEEE Trans. on CAD/ICAS. vol. 12. no. 9, pp, 1279-1286, Sept. 1993 https://doi.org/10.1109/43.240075
  6. Choi, Y.R., 'Synthesis of pipelined data paths:' Proc. of Int. Conf. on Computer-Aided Design. pp. 36-40. Jan. 1992
  7. Hwang K.S., Casavant A.E., Chang C.T. and Manuel A d'Abreu. 'Scheduling and Hardware Sharing in Pipelined Data Path,' Proc, of Int. Conf. Computer-Aided Design, pp. 24-27, 1989 https://doi.org/10.1109/ICCAD.1989.76897
  8. Paulin P.G. and Knight J.P., 'Force-directed scheduling for behavioral synthesis of ASIC's:' IEEE Trans. on Computer-Aided Design, vol. 8. pp. 661-679. March 1989 https://doi.org/10.1109/43.31522
  9. Verhaegh W.F.J, Lippens P.E.R.. Aarts E.H.L., Karst J.H.M., A van der Werf and J.L. van Meerbergen, 'Efficiency Improvements for Force-Directed Scheduling:' Proc, of Int. Conf. Computer-Aided Design, pp, 286-291. 1992 https://doi.org/10.1109/ICCAD.1992.279359
  10. D. Gajski, A. Wu, N. Dutt and S. Lin, HIGH-LEVEL SYNTHESIS Introduction to Chip and Syatem Design, PP.213-258, Kluwer Academic Publishers, 1992
  11. Lee T.F., Wu AC., Gajski D.D. and Lin Y.L., 'An effective methodology for functional pipelining,' Proc. of Int. Conf. Computer-Aided Design, pp. 230-233. 1992 https://doi.org/10.1109/ICCAD.1992.279369
  12. J. L. Wong. S. Megerian, and M. Potkonjak, 'Forward-Looking Objective Function: Concept & Applications in High Level Synthesis:' Proc, of the 39th Design Automation Conference, June 2002 https://doi.org/10.1109/DAC.2002.1012750
  13. S. Kung. H. Whitehouse and T. Kailath, VLSI and Modern Signal Processing' pp.258-264. Prentice Hall. 1985