DOI QR코드

DOI QR Code

A Design of Queue Architecture for Adaptive Routers

적응적 라우터를 위한 큐 구조 설계

  • 최영호 (건국대학교 전기공학과) ;
  • 박능수 (건국대학교 컴퓨터공학부) ;
  • 송용호 (한양대하교 정보통신대학 미디어통신공학)
  • Published : 2005.08.01

Abstract

This paper proposes DAMQWR and VCDAMQ architectures that enloit the full capabilities of adaptive routing. DAMQWR enables messages in congested channels to route through non-congested channels by using recruit registers while VCDAMQ dynamically assigns resources among virtual channels, resulting in better network traffic control. Through extensive simulations and analysis, this paper evaluates their effects on overall network cost and performance. These proposed queue architectures, VCDAMQ and DAMQWR are shown to appropriately support adaptive routing capability by dynamically and efficiently managing queue and network resources, increasing network performance. The results show that up to $20\%$ higher throughput can be obtained in comparison to traditional DAMQ designs.

본 논문은 적응적 망 경로 선택 기능을 최대한 활용하기 위하여 두 가지 새로운 큐 구조 DAMQWR와 VCDAMQ를 제안하였다. DAMQWR은 리쿠르트 레지스터를 사용하여 정체된 채널의 메시지를 비 정체 채널로 라우팅을 유도할 수 있게 하여주며 VCDAMQ는 가상 채널상의 교통량을 동적으로 지원하도록 함으로써 망의 흐름을 보다 원활하게 하여 준다. 시뮬레이션과 분석을 통하여 제안된 큐 구조의 특성과 성능을 평가하였고 그 결과 제안되어진 큐 구조들인 VCDAMQ와 DAMQWR 구조가 메모리 및 망의 자원을 효과적으로 사용하여 적응적 라우터에 가장 적합함을 알 수 있었으며, 실험결과에서 기존의 DAMQ에 비하여 최대 $20\%$까지 망의 통신 성능이 향상됨을 보였다.

Keywords

References

  1. K.V. Anjan, M.P. Timothy, An efficient, fully adaptive deadlock recovery scheme: DISHA, Proceedings of the 22nd International Symposium on Computer Architecture, IEEE Computer Society, Silver Spring, MD, pp.201-210, June, 1995
  2. J. Kim, Z. Liu, A. Chien, Compressionless routing: a framework for adaptive and fault-tolerant routing, IEEE Trans. Parallel Distributed Syst. Vol.8, No.3, pp.229-244, March, 1997 https://doi.org/10.1109/71.584089
  3. M.P. Timothy, Flexible and efficient routing based on progressive deadlock recovery, IEEE Trans. Comput. Vol.48, No.7, July, 1999 https://doi.org/10.1109/12.780873
  4. J. Ding, L.N. Bhuyan, Performance evaluation of multistage interconnection networks with finite buffers, Proceedings of 1991 International Conference on Parallel Processing, Vol.1, pp.592-599, 1991
  5. P. Goli, V. Kumar, Performance of a crosspoint buffered ATM switch fabric, Proceedings of INFOCOM'92, pp.3D.1.1-3D.1.10, 1992 https://doi.org/10.1109/INFCOM.1992.263582
  6. N. Ni, M. Pirvu, L. Bhuyan, Circular buffered switch design with wormhole routing and virtual channels, Proceedings of the International Conference on Computer Design, pp.466-473, 1998 https://doi.org/10.1109/ICCD.1998.727090
  7. J. Park, B.W. O'Krafka, S. Vassiliadis, J. Delgado-Frias, Design and evaluation of a DAMQ multiprocessor network with selfcompacting buffers, Proceedings of Supercomputing'94, pp.713-722, 1994
  8. F. Petrini, Wu chun Feng, Adolfy Hoisie, Salvador Coli, Eitan Frachtenberg, The quadrics network high-performance clustering technology, IEEE Micro, Vol.22, No.1, pp.2-13, January, 2002 https://doi.org/10.1109/MM.2002.988663
  9. R. Sivaram, C.B. Stunkel, D.K. Panda, A high-performance switch architecture using input queueing, Proceedings of the IPPS/SPDP, IEEE Computer Society Press, Silver Spring, MD, pp.134-143, March, 1998 https://doi.org/10.1109/IPPS.1998.669901
  10. C.B. Stunkel et al., The SP2 high-performance switch, IBM Syst. J. Vol.34, No.2, pp.185-204, 1995 https://doi.org/10.1147/sj.342.0185
  11. Y. Tamir, L. Frazier, Dynamically-allocated multi-queue buffers for VLSI communication switches, IEEE Trans. Comput. Vol.41, No.6, pp.725-737, June, 1992 https://doi.org/10.1109/12.144624
  12. M. Galles, Spider: a high speed network interconnect, IEEE Micro, pp.34-39, February, 1997 https://doi.org/10.1109/40.566196
  13. Shubhendu S. Mukherjee, Peter Bannon, L. Steven, Aaron Spink, David Webb, The alpha 21364 network architecture, Symposium on High Performance Interconnects (HOT Interconnects 9), IEEE Computer Society Press, Silver Spring, MD, pp.113-117, August, 2001 https://doi.org/10.1109/HIS.2001.946702
  14. L.S. Steven, M.T. Gregory, Optimized routing in the cray T3D, Proceedings of the Workshop on Parallel Computer Routing and Communication, pp.281-294, May, 1994
  15. L.S. Steven, M.T. Gregory, The cray T3E network: adaptive routing in a high performance 3D torus, Proceedings of the Symposium on Hot Interconnects, IEEE Computer Society, Silver Spring, MD, pp.147-156, August, 1996
  16. W. Dally, Virtual channel flow control, IEEE Trans. Parallel Distributed Syst. Vol.3, No.2, pp.194-205, March, 1992 https://doi.org/10.1109/71.127260
  17. W. Dally, H. Aoki, Deadlock-free adaptive routing in multicomputer networks using virtual channels, IEEE Trans. Parallel Distributed Syst. Vol.4, No.4, pp.466-475, April, 1993 https://doi.org/10.1109/71.219761
  18. Andrew A. Chien, A cost and speed model for k-ary n-Cube wormhole routers, IEEE Trans. Parallel Distributed Syst. Vol.9, No.2, pp.150-162, February, 1998 https://doi.org/10.1109/71.663877
  19. Li-Shiuan Peh, W. Dally, A delay model for router microarchitectures, IEEE Micro Vol.21, No.1, pp.26-34, Jan., 2001 https://doi.org/10.1109/40.903059
  20. SMART Interconnects Group. Flexsim 1.2 Simulator, University of Southern California, 1997; www.usc.edu/dept/ceng/pinkston/SMART.html
  21. M.P. Timothy, Yungho Choi, Mongkol Raksapatcharawong. Architecture and optoelectronic implementation of the WARRP router, Proceedings of the 5th Symposium on Hot Interconnects, IEEE Computer Society, Silver Spring, MD, pp.181-189, August, 1997