ASIP Instructions and Their Hardware Architecture for H.264/AVC

  • Lee, Jung-H. (School of Electrical and Computer Engineering, Ajou University) ;
  • Kim, Sung-D. (School of Electrical and Computer Engineering, Ajou University) ;
  • Sunwoo, Myung-H. (School of Electrical and Computer Engineering, Ajou University)
  • 발행 : 2005.12.31

초록

H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced about $20{\sim}25%$. This paper also proposes new instructions for the integer transform. The proposed instructions can execute one dimension forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.

키워드

참고문헌

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