JSTS:Journal of Semiconductor Technology and Science

  • 제4권3호
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  • Pages.196-203
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  • 2004
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals

  • Gutmann, R.J. (Center for Integrated Electronics Rensselaer Polytechnic Institute) ;
  • Zeng, A.Y. (Center for Integrated Electronics Rensselaer Polytechnic Institute) ;
  • Devarajan, S. (Center for Integrated Electronics Rensselaer Polytechnic Institute) ;
  • Lu, J.Q. (Center for Integrated Electronics Rensselaer Polytechnic Institute) ;
  • Rose, K. (Center for Integrated Electronics Rensselaer Polytechnic Institute)
  • 발행 : 2004.09.30
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초록

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

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참고문헌

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